`timescale 1ns/1ps;
module top1(
);
reg a=1'b0x;
reg b=1;
wire c;
wire d;
wire f;
assign c=a&b;
assign d=a|b
与或非门输入x和z,输出状态
最新推荐文章于 2023-03-23 20:23:14 发布
`timescale 1ns/1ps;
module top1(
);
reg a=1'b0x;
reg b=1;
wire c;
wire d;
wire f;
assign c=a&b;
assign d=a|b