FPGA--点阵屏模块（代码）

最新推荐文章于 2024-07-13 22:30:16 发布
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最新推荐文章于 2024-07-13 22:30:16 发布
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分类专栏： FPGA ZYNQ ECO开发板文章标签： fpga开发
本文链接：https://blog.csdn.net/yandadzf/article/details/139144698
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`timescale 1ns / 1ps



module dzp_mk(
    input       clk     ,
    input       rst_n   ,
    input [10:0]   cnt_number,   //显示的模式
    input  [2:0]    mode,   //流动方向
    input  [31:0]   speed,  //屏幕移动完所需要的时间
    
    output reg   DI      ,      //led状态 串行数据输入端口
    output reg   RCK      ,      //上升沿将数据放入LED
    output       SCK    //5M        50M->5M;    锁相环（PLL）     //时钟---当时钟一个上升沿时 点阵屏锁存器保存一位DI电平信息
    );
wire        locked          ;
wire            en          ;//点阵屏工作的开关
assign en = rst_n & locked;
reg [15:0]  data_reg ;
reg [3 :0]  cnt_bit;    //用以记录第几bit


//**********************************///
reg [7:0] data_hsm;
reg [7:0] data [7:0];


 
parameter delay_1ms = 50_000_000/1000;
reg [31:0]cnt_1ms ;
reg [3:0]   cnt_number_h;
always @(posedge clk )
if (!rst_n)
    cnt_1ms <= 0;
else if (cnt_1ms >= delay_1ms)
    cnt_1ms <= 0;
else 
    cnt_1ms <= cnt_1ms + 1;


always @(posedge clk )
if (!rst_n)
    cnt_number_h <=0;
else if(cnt_number_h >= 8)
    cnt_number_h <= 0;
else if (cnt_1ms == delay_1ms -1)
    cnt_number_h <= cnt_number_h + 1;
else
    cnt_number_h <= cnt_number_h ;

always @(posedge clk)
if(!rst_n)
    data_hsm <= 8'b0000_0001;
else if(cnt_1ms == delay_1ms -1)
    data_hsm <= {data_hsm[6:0],data_hsm[7]};
else
    data_hsm <= data_hsm;
    
always @(posedge clk )
if (!rst_n)
    data_reg <= 0;
else
    data_reg <= {data_hsm[7:0],data[cnt_number_h]};
        

//**********************************/


/产生驱动时钟  SCK   

clk_wiz_0 instance_name
   (
    // Clock out ports
    .clk_out1(SCK),     // output clk_out1
    // Status and control signals
    .resetn(rst_n), // input resetn
    .locked(locked),    //标志输出时钟的稳定   // output locked
   // Clock in ports
    .clk_in1(clk));      // input clk_in1


//clock     == 时钟
//can_bit
always @(posedge SCK)
if(!rst_n)
    cnt_bit <= 0;
else if (en == 1 && cnt_bit >= 4'd15)
    cnt_bit <= 0;
else if (en == 1)
    cnt_bit <= cnt_bit + 1;
else
    cnt_bit <= 0;

//DI赋值
always @(negedge SCK)
if(!rst_n)
    DI<= 0;
else if (en)begin
    DI <= data_reg[cnt_bit];
    end
else
    DI <=0;
    
    
//*************************//
//RCK
reg [3:0]       cnt;    ///0-9
always@(posedge clk )
if(!rst_n )
    cnt <= 0;
else if(en == 1)begin
    if(cnt_bit == 0)
        if(cnt >= 9)    cnt<=0;
        else            cnt <= cnt +1;
     else
        cnt <= 0;
    end
else
    cnt <= 0;

//RXK=0  传数据
always @(posedge clk)
if (!rst_n)
    RCK<=1;
else if(en==1)begin
    if(cnt_bit == 0 && cnt >= 5 && cnt<=8)
        RCK<= 1;
    else
        RCK <= 0;    
    end
else
    RCK <= 1;


//**********************************************/


/***********数字库*******************
wire [7:0] number_1 [7:0];
assign number_1[0] = 8'hFF  ;
assign number_1[1] = 8'hEF  ;
assign number_1[2] = 8'hCF  ;
assign number_1[3] = 8'hEF  ;
assign number_1[4] = 8'hEF  ;
assign number_1[5] = 8'hEF  ;
assign number_1[6] = 8'hC7  ;
assign number_1[7] = 8'hFF  ;

wire [7:0] number_2 [7:0];
assign number_2[0] = 8'hFF   ;
assign number_2[1] = 8'hC7   ;
assign number_2[2] = 8'hF7   ;
assign number_2[3] = 8'hC7   ;
assign number_2[4] = 8'hDF   ;
assign number_2[5] = 8'hC7   ;
assign number_2[6] = 8'hFF   ;
assign number_2[7] = 8'hFF   ;


wire [7:0] number_3 [7:0];
assign number_3[0] = 8'hFF   ;
assign number_3[1] = 8'hC7   ;
assign number_3[2] = 8'hF7   ;
assign number_3[3] = 8'hC7   ;
assign number_3[4] = 8'hF7   ;
assign number_3[5] = 8'hC7   ;
assign number_3[6] = 8'hFF   ;
assign number_3[7] = 8'hFF   ;

wire [7:0] number_4 [7:0];
assign number_4[0] = 8'hFF   ;
assign number_4[1] = 8'hF7   ;
assign number_4[2] = 8'hE7   ;
assign number_4[3] = 8'hD7   ;
assign number_4[4] = 8'h81   ;
assign number_4[5] = 8'hF7   ;
assign number_4[6] = 8'hF7   ;
assign number_4[7] = 8'hFF   ;


wire [7:0] number_5 [7:0];
assign number_5[0] = 8'hFF   ;
assign number_5[1] = 8'hC7   ;
assign number_5[2] = 8'hDF   ;
assign number_5[3] = 8'hC7   ;
assign number_5[4] = 8'hF7   ;
assign number_5[5] = 8'hC7   ;
assign number_5[6] = 8'hFF   ;
assign number_5[7] = 8'hFF   ;


wire [7:0] number_6 [7:0];
assign number_6[0] = 8'hFF   ;
assign number_6[1] = 8'hC7   ;
assign number_6[2] = 8'hDF   ;
assign number_6[3] = 8'hC7   ;
assign number_6[4] = 8'hD7   ;
assign number_6[5] = 8'hC7   ;
assign number_6[6] = 8'hFF   ;
assign number_6[7] = 8'hFF   ;


wire [7:0] number_7 [7:0];
assign number_7[0] = 8'hFF   ;
assign number_7[1] = 8'hC7   ;
assign number_7[2] = 8'hF7   ;
assign number_7[3] = 8'hF7   ;
assign number_7[4] = 8'hF7   ;
assign number_7[5] = 8'hF7   ;
assign number_7[6] = 8'hFF   ;
assign number_7[7] = 8'hFF   ;



wire [7:0] number_8 [7:0];
assign number_8[0] = 8'hFF   ;
assign number_8[1] = 8'hC7   ;
assign number_8[2] = 8'hD7   ;
assign number_8[3] = 8'hC7   ;
assign number_8[4] = 8'hD7   ;
assign number_8[5] = 8'hC7   ;
assign number_8[6] = 8'hFF   ;
assign number_8[7] = 8'hFF   ;



wire [7:0] number_9 [7:0];
assign number_9[0] = 8'hFF   ;
assign number_9[1] = 8'hC7   ;
assign number_9[2] = 8'hD7   ;
assign number_9[3] = 8'hC7   ;
assign number_9[4] = 8'hF7   ;
assign number_9[5] = 8'hC7   ;
assign number_9[6] = 8'hFF   ;
assign number_9[7] = 8'hFF   ;


wire [7:0] number_0 [7:0];
assign number_0[0] = 8'hFF   ;
assign number_0[1] = 8'hC7   ;
assign number_0[2] = 8'hD7   ;
assign number_0[3] = 8'hD7   ;
assign number_0[4] = 8'hD7   ;
assign number_0[5] = 8'hC7   ;
assign number_0[6] = 8'hFF   ;
assign number_0[7] = 8'hFF   ;

//10        SDK
wire [63:0] pattern_1I = 64'hEF_C7_D7_01_D7_C7_EF_EF;
wire [7:0] pattern_1 [7:0];
assign pattern_1[7] = pattern_1I[7:0]   ;
assign pattern_1[6] = pattern_1I[15:8]   ;
assign pattern_1[5] = pattern_1I[23:16]   ;
assign pattern_1[4] = pattern_1I[31:24]   ;
assign pattern_1[3] = pattern_1I[39:32]   ;
assign pattern_1[2] = pattern_1I[47:40]   ;
assign pattern_1[1] = pattern_1I[55:48]   ;
assign pattern_1[0] = pattern_1I[63:56]   ;


wire [63:0] pattern_2I = 64'hFF_99_00_00_81_C3_E7_FF;
wire [7:0] pattern_2 [7:0];
assign pattern_2[7] = pattern_2I[7:0]   ;
assign pattern_2[6] = pattern_2I[15:8]   ;
assign pattern_2[5] = pattern_2I[23:16]   ;
assign pattern_2[4] = pattern_2I[31:24]   ;
assign pattern_2[3] = pattern_2I[39:32]   ;
assign pattern_2[2] = pattern_2I[47:40]   ;
assign pattern_2[1] = pattern_2I[55:48]   ;
assign pattern_2[0] = pattern_2I[63:56]   ;



//**********************************************/



//速度显示
reg [31:0] speed_cnt ;
wire [31:0] speed_delay = speed/8;

//数据切换
always @(posedge clk)
if(!rst_n)
    speed_cnt<=0;
else if(speed_cnt >= speed_delay)
    speed_cnt <= 0;
else
    speed_cnt <= speed_cnt + 1;


parameter left = 1; //左移
parameter right = 2;//右移
parameter up    = 3;//上移
parameter decline = 4;//下移
parameter stop = 0;   //不移动

reg [31:0] zq_cnt_number;
reg zt;
always @(posedge clk)
if(!rst_n)begin
    zq_cnt_number <= 0;
    zt <= 0;
end
else if(zq_cnt_number != cnt_number)begin
    zq_cnt_number <= cnt_number;
    zt <= 1;
end
else    begin
    zt <= 0;
    zq_cnt_number <= zq_cnt_number;
end
    


always @(posedge clk)
if(!rst_n)begin
    data[0] <= 0;
    data[1] <= 0;
    data[2] <= 0;
    data[3] <= 0;
    data[4] <= 0;
    data[5] <= 0;
    data[6] <= 0;
    data[7] <= 0;   
    end
else if(speed_cnt == speed_delay - 1)begin
        case(mode)
            stop:begin
                data[0] <= data[0];
                data[1] <= data[1];
                data[2] <= data[2];
                data[3] <= data[3];
                data[4] <= data[4];
                data[5] <= data[5];
                data[6] <= data[6];
                data[7] <= data[7];   
                end
            left     :begin
                data[0] <= {data[0][6:0],data[0][7]};
                data[1] <= {data[1][6:0],data[1][7]};
                data[2] <= {data[2][6:0],data[2][7]};
                data[3] <= {data[3][6:0],data[3][7]};
                data[4] <= {data[4][6:0],data[4][7]};
                data[5] <= {data[5][6:0],data[5][7]};
                data[6] <= {data[6][6:0],data[6][7]};
                data[7] <= {data[7][6:0],data[7][7]};   
                end
            right    :begin
                data[0] <= {data[0][0],data[0][7:1]};
                data[1] <= {data[1][0],data[1][7:1]};
                data[2] <= {data[2][0],data[2][7:1]};
                data[3] <= {data[3][0],data[3][7:1]};
                data[4] <= {data[4][0],data[4][7:1]};
                data[5] <= {data[5][0],data[5][7:1]};
                data[6] <= {data[6][0],data[6][7:1]};
                data[7] <= {data[7][0],data[7][7:1]};   
                end
            up       :begin
                data[0] <= data[1];
                data[1] <= data[2];
                data[2] <= data[3];
                data[3] <= data[4];
                data[4] <= data[5];
                data[5] <= data[6];
                data[6] <= data[7];
                data[7] <= data[0];   
                end
            decline  :begin
                data[0] <= data[7];
                data[1] <= data[0];
                data[2] <= data[1];
                data[3] <= data[2];
                data[4] <= data[3];
                data[5] <= data[4];
                data[6] <= data[5];
                data[7] <= data[6];   
                end
            
            default:begin
                data[0] <= data[0];
                data[1] <= data[1];
                data[2] <= data[2];
                data[3] <= data[3];
                data[4] <= data[4];
                data[5] <= data[5];
                data[6] <= data[6];
                data[7] <= data[7];   
                end
        endcase
    end
else if(zt == 1)    //图案发生变化
    case(cnt_number)
    1:begin
    data[0] <= number_1[0];
    data[1] <= number_1[1];
    data[2] <= number_1[2];
    data[3] <= number_1[3];
    data[4] <= number_1[4];
    data[5] <= number_1[5];
    data[6] <= number_1[6];
    data[7] <= number_1[7];   
    end
    2:begin
    data[0] <= number_2[0];
    data[1] <= number_2[1];
    data[2] <= number_2[2];
    data[3] <= number_2[3];
    data[4] <= number_2[4];
    data[5] <= number_2[5];
    data[6] <= number_2[6];
    data[7] <= number_2[7];   
    end
    3:begin
    data[0] <= number_3[0];
    data[1] <= number_3[1];
    data[2] <= number_3[2];
    data[3] <= number_3[3];
    data[4] <= number_3[4];
    data[5] <= number_3[5];
    data[6] <= number_3[6];
    data[7] <= number_3[7];   
    end
    4:begin
    data[0] <= number_4[0];
    data[1] <= number_4[1];
    data[2] <= number_4[2];
    data[3] <= number_4[3];
    data[4] <= number_4[4];
    data[5] <= number_4[5];
    data[6] <= number_4[6];
    data[7] <= number_4[7];   
    end
    5:begin
    data[0] <= number_5[0];
    data[1] <= number_5[1];
    data[2] <= number_5[2];
    data[3] <= number_5[3];
    data[4] <= number_5[4];
    data[5] <= number_5[5];
    data[6] <= number_5[6];
    data[7] <= number_5[7];   
    end
    6:begin
    data[0] <= number_6[0];
    data[1] <= number_6[1];
    data[2] <= number_6[2];
    data[3] <= number_6[3];
    data[4] <= number_6[4];
    data[5] <= number_6[5];
    data[6] <= number_6[6];
    data[7] <= number_6[7];   
    end
    7:begin
    data[0] <= number_7[0];
    data[1] <= number_7[1];
    data[2] <= number_7[2];
    data[3] <= number_7[3];
    data[4] <= number_7[4];
    data[5] <= number_7[5];
    data[6] <= number_7[6];
    data[7] <= number_7[7];   
    end
    8:begin
    data[0] <= number_8[0];
    data[1] <= number_8[1];
    data[2] <= number_8[2];
    data[3] <= number_8[3];
    data[4] <= number_8[4];
    data[5] <= number_8[5];
    data[6] <= number_8[6];
    data[7] <= number_8[7];   
    end
    9:begin
    data[0] <= number_9[0];
    data[1] <= number_9[1];
    data[2] <= number_9[2];
    data[3] <= number_9[3];
    data[4] <= number_9[4];
    data[5] <= number_9[5];
    data[6] <= number_9[6];
    data[7] <= number_9[7];   
    end
    0:begin
    data[0] <= number_0[0];
    data[1] <= number_0[1];
    data[2] <= number_0[2];
    data[3] <= number_0[3];
    data[4] <= number_0[4];
    data[5] <= number_0[5];
    data[6] <= number_0[6];
    data[7] <= number_0[7];  
    end 
    10: begin
    data[0] <=pattern_1[0] ;
    data[1] <=pattern_1[1] ;
    data[2] <=pattern_1[2] ;
    data[3] <=pattern_1[3] ;
    data[4] <=pattern_1[4] ;
    data[5] <=pattern_1[5] ;
    data[6] <=pattern_1[6] ;
    data[7] <=pattern_1[7] ; 
    end
    
    11: begin
    data[0] <=pattern_2[0] ;
    data[1] <=pattern_2[1] ;
    data[2] <=pattern_2[2] ;
    data[3] <=pattern_2[3] ;
    data[4] <=pattern_2[4] ;
    data[5] <=pattern_2[5] ;
    data[6] <=pattern_2[6] ;
    data[7] <=pattern_2[7] ; 
    end
    default:begin
    data[0] <= data[0];
    data[1] <= data[1];
    data[2] <= data[2];
    data[3] <= data[3];
    data[4] <= data[4];
    data[5] <= data[5];
    data[6] <= data[6];
    data[7] <= data[7];   
    end
    endcase
else begin
    data[0] <= data[0];
    data[1] <= data[1];
    data[2] <= data[2];
    data[3] <= data[3];
    data[4] <= data[4];
    data[5] <= data[5];
    data[6] <= data[6];
    data[7] <= data[7];   
    end

endmodule