【2022.04西南交大数电实验】
module yck_1716_2(codeout,clk,en,Q);
input clk,en;
output [2: 0] Q;
output [6: 0] codeout;
yck_1716_2_1 a(clk,en,Q);
yck_1716_2_2 b(codeout, Q);
endmodule
module yck_1716_2_1(clk,en,Q);
input clk,en;
output reg[2:0] Q;
always@(posedge clk)
begin
if(en == 1'b1)
begin
if(Q < 3'd6)
Q <= Q + 1'b1;
else
Q <= 0;
end
else
Q <=Q;
end
endmodule
module yck_1716_2_2(codeout, Q);
input[2: 0] Q;
output reg[6: 0] codeout;
always @ (*) //用always块语句描述逻辑
begin
case (Q)
3'd0: codeout <= 7'b0000001;
3'd1: codeout <= 7'b0000011;
3'd2: codeout <= 7'b0000111;
3'd3: codeout <= 7'b0001111;
3'd4: codeout <= 7'b0011111;
3'd5: codeout <= 7'b0111111;
3'd6: codeout <= 7'b0000000;
default: codeout <= 7'bx;
endcase
end
endmodule