HDLBits note(1)

1.Step one

problem statement

Build a circuit with no inputs and one output. That output should always drive 1 (or logic high).

module top_module( output one );

// Insert your code here
    assign one = 1;

endmodule

2.Zero

problem statement

Build a circuit with no inputs and one output that outputs a constant 0

module top_module(
    output zero
);// Module body starts after semicolon
    assign zero=0;

endmodule

3.wires

problem statement

Your task is to create a wire (in green) by adding an assign statement to connect in to out. The parts outside the box are not your concern, but you should know that your circuit is tested by connecting signals from our test harness to the ports on your top_module.

module top_module( input in, output out );

	assign out=in;

endmodule

Expected solution length: Around 1 line.

4. Wires4

problem statement

Create a module with 3 inputs and 4 outputs that behaves like wires that makes these connections:

a -> w
b -> x
b -> y
c -> z

Expected solution length: Around 4 lines.

module top_module( 
    input a,b,c,
    output w,x,y,z );
    assign w=a;
    assign x=b;
    assign y=b;
    assign z=c;

endmodule

5. Notgate

problem statement

Create a module that implements a NOT gate.

Use an assign statement. The assign statement will continuously drive the inverse of in onto wire out.

Verilog has separate bitwise-NOT (~) and logical-NOT (!) operators, like C. Since we're working with a one-bit here, it doesn't matter which we choose.

module top_module( input in, output out );
	assign out=~in;
endmodule

6.andgate

problem statement

Create a module that implements an AND gate.

Verilog has separate bitwise-AND (&) and logical-AND (&&) operators, like C. Since we're working with a one-bit here, it doesn't matter which we choose.

module top_module( 
    input a, 
    input b, 
    output out );
	assign out=a&b;
endmodule

7. Norgate

problem statement

Create a module that implements a NOR gate. A NOR gate is an OR gate with its output inverted. A NOR function needs two operators when written in Verilog.

Verilog has separate bitwise-OR (|) and logical-OR (||) operators, like C. Since we're working with a one-bit here, it doesn't matter which we choose.

module top_module( 
    input a, 
    input b, 
    output out );
    assign out=~(a|b);
endmodule

8. Xnorgate

problem statement

Create a module that implements an XNOR gate.

The bitwise-XOR operator is ^. There is no logical-XOR operator.

module top_module( 
    input a, 
    input b, 
    output out );
    assign out=~(a^b);
endmodule

9. Wire decl

problem statement

Implement the following circuit. Create two intermediate wires (named anything you want) to connect the AND and OR gates together. Note that the wire that feeds the NOT gate is really wire out, so you do not necessarily need to declare a third wire here. Notice how wires are driven by exactly one source (output of a gate), but can feed multiple inputs.

If you're following the circuit structure in the diagram, you should end up with four assign statements, as there are four signals that need a value assigned.

`default_nettype none
module top_module(
    input a,
    input b,
    input c,
    input d,
    output out,
    output out_n   ); 
    assign out=(a&b)||(c&d);
    assign out_n=~((a&b)||(c&d));
endmodule

10. 7458

problem statement

The 7458 is a chip with four AND gates and two OR gates. This problem is slightly more complex than 7420.

Create a module with the same functionality as the 7458 chip. It has 10 inputs and 2 outputs. You may choose to use an assign statement to drive each of the output wires, or you may choose to declare (four) wires for use as intermediate signals, where each internal wire is driven by the output of one of the AND gates. For extra practice, try it both ways.

module top_module ( 
    input p1a, p1b, p1c, p1d, p1e, p1f,
    output p1y,
    input p2a, p2b, p2c, p2d,
    output p2y );
	wire in_1,in_2,in_3,in_4;
    assign in_1=p2a&p2b;
    assign in_2=p2c&p2d;
    assign in_3=p1a&p1b&p1c;
    assign in_4=p1d&p1f&p1e;
    assign p1y=in_3|in_4;
    assign p2y=in_1|in_2;

endmodule

//真是没想到CSDN竟然不支持直接粘贴截图，这太傻了，转战知乎好了。