verilog基础1

module top_module (
    input in,              // Declare an input wire named "in"
    output out             // Declare an output wire named "out"
);
    wire not_in;           // Declare a wire named "not_in"
    assign out = ~not_in;  // Assign a value to out (create a NOT gate).
    assign not_in = ~in;   // Assign a value to not_in (create another NOT gate).

assgin 连续赋值语句

wire语句：

例子一：

A continuous assignment assigns the right side to the left side continuously, so any change to the RHS is immediately seen in the LHS 

module top module( input in, output out );
assign out=in;
endmodule

例子二：

拼接运算符：位拼接运算符：{}

功能：将两个或者多个信号的某些位拼接起来

{信号1的某位，信号2的某几位...信号n的某几位.}

{3{a,b}}={ {a,b},{a,b},{a,b}}={a,b,a,b,a,b}

The concatenation operator { signal1, signal2, signal3, ... } would be useful here.

module top module(    input a,b,c,    output w,x,y,z );  
assign {w,x,y,z}={a,b,b,c};
endmodule

Notgete(非门)：