Finding bugs in code

This 8-bit wide 2-to-1 multiplexer doesn't work. Fix the bug(s).

module top_module (
    input sel,
    input [7:0] a,
    input [7:0] b,
    output out  );

    assign out = (~sel & a) | (sel & b);

endmodule

从上面的代码中我们可以看到，输出的out信号位宽不对，其次多路选择的表达式有误，按上图代码中的取法只能取出1bit。

module top_module (
    input sel,
    input [7:0] a,
    input [7:0] b,
    output [7:0] out  );
    assign out=sel?a:b;
endmodule

This three-input NAND gate doesn't work. Fix the bug(s).

You must use the provided 5-input AND gate:

module andgate ( output out, input a, input b, input c, input d, input e );

module top_module (input a, input b, input c, output out);//

    andgate inst1 ( a, b, c, out );

endmodule

由上面可供调用的模块可见，输入输出的对应关系不对，且参数数量也不对，代码改正如下：

module top_module (input a, input b, input c, output out);//
wire ot;
    andgate inst1 (ot,a,b,c,1,1);
assign out=~ot;
endmodule

This 4-to-1 multiplexer doesn't work. Fix the bug(s).

You are provided with a bug-free 2-to-1 multiplexer:

module mux2 (
    input sel,
    input [7:0] a,
    input [7:0] b,
    output [7:0] out
);

module top_module (
    input [1:0] sel,
    input [7:0] a,
    input [7:0] b,
    input [7:0] c,
    input [7:0] d,
    output [7:0] out  ); //

    wire mux0, mux1;
    mux2 mux0 ( sel[0],    a,    b, mux0 );
    mux2 mux1 ( sel[1],    c,    d, mux1 );
    mux2 mux2 ( sel[1], mux0, mux1,  out );

endmodule

sel[1]区分不了c和d，此处应该还是sel[0]。此外例化名与变量名不能重复；且wire信号的位宽也不对

module top_module (
    input [1:0] sel,
    input [7:0] a,
    input [7:0] b,
    input [7:0] c,
    input [7:0] d,
    output [7:0] out  ); //
    wire [7:0] mux00, mux11;
    mux2 mux0 (sel[0],a,b, mux00 );
    mux2 mux1 (sel[0],c,d, mux11 );
    mux2 mux2 (sel[1],mux00,mux11,out );
endmodule

 The following adder-subtractor with zero flag doesn't work. Fix the bug(s).

// synthesis verilog_input_version verilog_2001
module top_module ( 
    input do_sub,
    input [7:0] a,
    input [7:0] b,
    output reg [7:0] out,
    output reg result_is_zero
);//

    always @(*) begin
        case (do_sub)
          0: out = a+b;
          1: out = a-b;
        endcase

        if (~out)
            result_is_zero = 1;
    end

endmodule

因为result_is_zero为reg型，当其为1后一直为1，因为没有其他状态能使其改变，且需锁存状态，因为if未遍历所有状态

// synthesis verilog_input_version verilog_2001
module top_module ( 
    input do_sub,
    input [7:0] a,
    input [7:0] b,
    output reg [7:0] out,
    output reg result_is_zero
);//
    always @(*) begin
        case (do_sub)
          0:out=a+b;
          1:out=a-b;
        endcase
        if (out==8'b0)
            result_is_zero=1;
        else
            result_is_zero=0;
    end
endmodule

 This combinational circuit is supposed to recognize 8-bit keyboard scancodes for keys 0 through 9. It should indicate whether one of the 10 cases were recognized (valid), and if so, which key was detected. Fix the bug(s).

module top_module (
    input [7:0] code,
    output reg [3:0] out,
    output reg valid=1 );//

     always @(*)
        case (code)
            8'h45: out = 0;
            8'h16: out = 1;
            8'h1e: out = 2;
            8'd26: out = 3;
            8'h25: out = 4;
            8'h2e: out = 5;
            8'h36: out = 6;
            8'h3d: out = 7;
            8'h3e: out = 8;
            6'h46: out = 9;
            default: valid = 0;
        endcase

endmodule

默认输出valid=1不能按上图所示的编写代码，默认的输入可以；其次进制8'd26需改成8进制。6'h46改为8‘h46。

module top_module (
    input [7:0] code,
    output reg [3:0] out,
    output reg valid);//
    always @(*) begin
        case (code)
            8'h45: out = 4'd0;
            8'h16: out = 4'd1;
            8'h1e: out = 4'd2;
            8'h26: out = 4'd3;
            8'h25: out = 4'd4;
            8'h2e: out = 4'd5;
            8'h36: out = 4'd6;
            8'h3d: out = 4'd7;
            8'h3e: out = 4'd8;
            8'h46: out = 4'd9;
            default: out=4'd0;
        endcase
        if(out==4'd0&&code!=8'h45)
            valid=1'b0;
        else
            valid=1'b1;
    end
endmodule