Verilog学习之Norgate

Create a module that implements a NOR gate. A NOR gate is an OR gate with its output inverted. A NOR function needs two operators when written in Verilog.

创建一个实现 NOR 门的模块。或非门是一个输出反相的或门。用 Verilog 编写的 NOR 函数需要两个运算符。

An assign statement drives a wire (or "net", as it's more formally called) with a value. This value can be as complex a function as you want, as long as it's a combinational (i.e., memory-less, with no hidden state) function. An assign statement is a continuous assignment because the output is "recomputed" whenever any of its inputs change, forever, much like a simple logic gate.

分配语句驱动带有值的线（或“网”，因为它更正式地称为）。这个值可以是你想要的复杂函数，只要它是