Verilog学习之Norgate

Create a module that implements a NOR gate. A NOR gate is an OR gate with its output inverted. A NOR function needs two operators when written in Verilog.

创建一个实现 NOR 门的模块。或非门是一个输出反相的或门。用 Verilog 编写的 NOR 函数需要两个运算符。

An assign statement drives a wire (or "net", as it's more formally called) with a value. This value can be as complex a function as you want, as long as it's a combinational (i.e., memory-less, with no hidden state) function. An assign statement is a continuous assignment because the output is "recomputed" whenever any of its inputs change, forever, much like a simple logic gate.

分配语句驱动带有值的线（或“网”，因为它更正式地称为）。这个值可以是你想要的复杂函数，只要它是一个组合（即，无记忆，没有隐藏状态）函数。分配语句是连续分配，因为只要其任何输入永远发生变化，就会“重新计算”输出，就像一个简单的逻辑门一样。

Module Declaration

module top_module( 
    input a, 
    input b, 
    output out );

Verilog has separate bitwise-OR (|) and logical-OR (||) operators, like C. Since we're working with a one-bit here, it doesn't matter which we choose.

Verilog 有单独的按位或 (|) 和逻辑或 (||) 运算符，就像 C 一样。由于我们在这里使用一位，所以我们选择哪个并不重要。

module top_module( 
    input a, 
    input b, 
    output out );
    assign out = a|b;

endmodule

 

module top_module( 
    input a, 
    input b, 
    output out );
    assign out = ~(a|b);

endmodule