verilog基础Module层次化

Module：

module mod_a ( input in1, input in2, output out );
    // Module body
endmodule

Connecting Signals to Module Ports

There are two commonly-used methods to connect a wire to a port: by position or by name.

By position

mod_a instance1 ( wa, wb, wc ); 

By name

mod_a instance2 ( .out(wc), .in1(wa), .in2(wb) ); 

module top_module ( input a, input b, output out );
    mod_a mod_a1(.out(out),.in1(a),.in2(b));
    //mod_a mod_a1(a,b,out);
endmodule

Module pos:

module mod_a ( output, output, input, input, input, input );

module top_module ( 
    input a, 
    input b, 
    input c,
    input d,
    output out1,
    output out2
);
    mod_a mod_a1(out1,out2,a,b,c,d);
endmodule

 Module name:

You are given the following module:(顺序不重要)

module top_module ( 
    input a, 
    input b, 
    input c,
    input d,
    output out1,
    output out2
);
    mod_a mod_a1(.in1(a),.in2(b),.in3(c),.in4(d),.out1(out1),.out2(out2));
endmodule