Sequential logic-shift registers

构建一个4bit的移位寄存器(右移)，含异步复位、同步加载和使能

• areset：让寄存器复位为0
• load：加载4bit数据到移位寄存器中，不移位
• ena：使能右移
• q：移位寄存器中的内容

• module top_module(
      input clk,
      input areset,  // async active-high reset to zero
      input load,
      input ena,
      input [3:0] data,
      output reg [3:0] q); 
      always @(posedge clk or posedge areset) begin
          if(areset) begin
             q<=4'b0;
          end
          else if(load) begin
             q <= data;
          end
          else if(ena) begin
              q<={1'b0,q[3:1]};
          end
          else begin
              q<=q;
          end
          end
  endmodule

  构建一个100位的左右旋转器，同步load，左右旋转需使能。旋转器从另一端输入移位的位元，不像移位器那样丢弃移位的位元而以零位移位。如果启用，旋转器就会旋转这些位，而不会修改或丢弃它们。

  load：加载100位的移位寄存器数据
  ena[1:0]：2’b01 右转1bit； 2’b10 左转1bit；其他情况不转
  q：旋转器内容

  module top_module(
      input clk,
      input load,
      input [1:0] ena,
      input [99:0] data,
      output reg [99:0] q); 
      always @(posedge clk) begin
          if(load) begin
              q<=data;
          end
          else begin
              case(ena) 
                  2'b01:q<={q[0],q[99:1]};
                  2'b10:q<={q[98:0],q[99]};
                  default:q<=q;
           endcase
          end
      end
  endmodule

  Build a 64-bit arithmetic shift register, with synchronous load. The shifter can shift both left and right, and by 1 or 8 bit positions, selected by amount.

  An arithmetic right shift shifts in the sign bit of the number in the shift register (q[63] in this case) instead of zero as done by a logical right shift. Another way of thinking about an arithmetic right shift is that it assumes the number being shifted is signed