PowerVR wiki


http://www.imgtec.com/powervr/sgx_series5.asp

http://en.wikipedia.org/wiki/PowerVR

PowerVR

From Wikipedia, the free encyclopedia

PowerVR is a division of Imagination Technologies (formerly VideoLogic) that develops hardware and software for 2D and 3D rendering, and for video encodingdecoding, associated image processing and DirectXOpenGL ESOpenVG, and OpenCL acceleration.

The PowerVR product line was originally introduced to compete in the desktop PC market for 3D hardware accelerators with a product with a better price/performance ratio than existing products like those from 3dfx Interactive. Rapid changes in that market, notably with the introduction of OpenGL and Direct3D, led to rapid consolidation; Most of the smaller players, like PowerVR, were pushed from the marketplace.

PowerVR responded by introducing new versions with low-power electronics that were aimed at the laptop computer market. Over time this developed into a series of designs that could be incorporated into system-on-a-chip architectures suitable for handheld device use. In this form, PowerVR is a leading vendor in the mobile space, found in many embedded systemspalmtops, and smartphones.

PowerVR accelerators are not manufactured by PowerVR, but instead their integrated circuit designs and patents are licensed to other companies, such as Texas Instruments,IntelNECRenesasSamsungSTMicroelectronicsFreescaleAppleNXP Semiconductors (formerly Philips Semiconductors), and many others.

Contents

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Technology [edit]

The PowerVR chipset uses a method of 3D rendering known as tile-based deferred rendering (often abbreviated as TBDR). As the polygon generating program feeds triangles to the PowerVR (driver), it stores them in memory in a triangle strip or an indexed format. Unlike other architectures, polygon rendering is (usually) not performed until all polygon information has been collated for the current frame. Furthermore, the expensive operations of texturing and shading of pixels (or fragments) is delayed, whenever possible, until the visible surface at a pixel is determined — hence rendering is deferred.

In order to render, the display is split into rectangular sections in a grid pattern. Each section is known as a tile. Associated with each tile is a list of the triangles that visibly overlap that tile. Each tile is rendered in turn to produce the final image.

Tiles are rendered using a process similar to ray-casting. Rays are cast[dubious ] onto the triangles associated with the tile and a pixel is rendered from the triangle closest to the camera. The PowerVR hardware typically calculates the depths associated with each polygon for one tile row in 1 cycle.[dubious ]

This method has the advantage that, unlike a more traditional z-buffered rendering pipeline[neutrality is disputed], no calculations need to be made to determine what a polygon looks like in an area where it is obscured by other geometry. It also allows for correct rendering of partially transparent polygons, independent of the order in which they are processed by the polygon producing application. (This capability was only implemented in Series 2 and one MBX variant. It is generally not included for lack of API support and cost reasons.) More importantly, as the rendering is limited to one tile at a time, the whole tile can be in fast onchip memory, which is flushed to video memory before processing the next tile. Under normal circumstances, each tile is visited just once per frame.

PowerVR is not the only pioneer of tile based deferred rendering, but the only one to successfully bring a TBDR solution to market. Microsoft also conceptualised the idea with their abandoned Talisman project. Gigapixel, a company that developed IP for tile-based deferred 3D graphics, was purchased by 3dfx, which in turn was subsequently purchased byNvidia. Nvidia currently has no official plans to pursue tile-based rendering.

Intel uses a similar concept in their integrated graphics solutions. However, their method, coined zone rendering, does not perform full hidden surface removal (HSR) and deferred texturing, therefore wasting fillrate and texture bandwidth on pixels that are not visible in the final image.

Recent advances in hierarchical Z-buffering have effectively incorporated ideas previously only used in deferred rendering, including the idea of being able to split a scene into tiles and of potentially being able to accept or reject tile sized pieces of polygon.

Today, the PowerVR software and hardware suite supports video encodingdecoding, associated image processing and Direct XOpenGL ESOpenVG, and OpenCLacceleration.[1]

Power VR chipsets [edit]

Series 1 (NEC) [edit]

VideoLogic Apocalypse 3Dx (NEC PowerVR PCX2 chip)

PowerVR's initial products were available as the OEM graphics on some Compaq models,[2] as an add-on card for other OEMs,[3] and the retail VideoLogic Apocalypse 3D[4] card.

Series 2 (NEC) [edit]

The second generation PowerVR2 ("PowerVR Series 2", chip codename "CLX2") chip found a market in the Dreamcast console between 1998 and 2001. As part of an internal competition at Sega to design the successor to the Saturn, the PowerVR2 was licensed to NEC and was chosen ahead of a rival design based on the 3dfx Voodoo 2. Thanks to the performance of the PowerVR2, several Dreamcast games such as Quake III Arena could rival their PC counterparts in quality and performance. However, the success of the Dreamcast meant that the PC variant, sold as Neon 250, appeared a year late to the market and was at that time mid-range at best.

Series 3 (STMicro) [edit]

Kyro II.

In 2001, STMicroelectronics adopted the third generation PowerVR3 for their STG4000 KYRO and STG 4500 KYRO II (displayed) chips. The STM PowerVR3 KYRO II, released in 2001, was able to rival the more expensive ATI Radeon DDR and NVIDIA GeForce 2 GTS on high in graphic benchmarks of the time, despite not having hardware Transform and lighting (T&L). As games were increasingly optimized for hardware T&L, the KYRO II lost its performance advantage.

Series 4 (STMicro) [edit]

STM's STG5000 chip, based upon the PowerVR4, did include hardware T&L but never came to commercial fruition. It and the KYRO 3 (2D/3D AIB) were shelved due to STMicro closing its graphics division.

MBX [edit]

PowerVR achieved great success in the mobile graphics market with its low power PowerVR MBX. MBX, and its SGX successors, are licensed by seven of the top ten semiconductor manufacturers including IntelTexas InstrumentsSamsungNECNXP Semiconductors,FreescaleRenesas and Sunplus. The chips are in use in many high-end cellphones including the original iPhoneNokia N95Sony Ericsson P1 and Motorola RIZR Z8, as well as some iPods.

There are two variants: MBX and MBX Lite. Both have the same feature set. MBX is optimized for speed and MBX Lite is optimized for low power consumption. MBX can be paired up with an FPU, Lite FPU, VGP Lite and VGP.

PowerVR Video Cores (MVED/VXD) and Video/Display Cores (PDP) [edit]

PowerVR's PDP series is used in some HDTVs, including the Sony BRAVIA.

Series 5 (SGX) [edit]

PowerVR's Series5 SGX series features pixelvertex, and geometry shader hardware, supporting OpenGL ES 2.0 and DirectX 10.1 with Shader Model 4.1.

The SGX GPU core is included in several popular systems-on-chip (SoC) used in many portable devices. Apple uses the A4 (manufactured by Samsung) in their iPhone 4iPad,iPod touch, and Apple TVTexas InstrumentsOMAP 3 and 4 series SoC's are used in the BlackBerry PlayBookNokia N900Sony Ericsson VivazMotorola Droid/Milestone,Motorola Defy, Motorola RAZR D1/D3, Droid Bionic, Archos 70Palm PreSamsung Galaxy SLGalaxy NexusOpen Pandora, and others. Samsung produces the HummingbirdSoC and uses it in their Samsung Galaxy SGalaxy TabSamsung Wave S8500 Samsung Wave II S8530, and Meizu M9 devices.

Intel uses the SGX 540 in its Medfield platform.[5]

Series 5XT (SGXMP) [edit]

PowerVR Series5XT SGXMP chips are multi-core variants of the SGX series with some updates. It is included in the PlayStation Vita portable gaming device with the MP4+ Model of the PowerVR SGX543, the only intended difference, aside from the + indicating features customized for Sony, is the cores, where MP4 denotes 4 cores (quad-core) whereas the MP8 denotes 8 cores (octo-core). The Allwinner A31 (quad-core mobile application processor) features the dual-core SGX544 MP2. The Apple iPad 2 and iPhone 4S with the A5SoC also feature a dual-core SGX543MP2. The iPad (3rd generation) A5X SoC features the quad-core SGX543MP4.[6] The iPhone 5 A6 SoC features the tri-core SGX543MP3. TheiPad (4th generation) A6X SoC features the quad-core SGX554MP4. The Exynos variant of the Samsung Galaxy S4 sports the tri-core SGX544MP3 clocked at 533 MHz

Series 6 (Rogue) [edit]

PowerVR Series6 is Imagination’s next generation architecture, codenamed ‘Rogue’. ST-Ericsson has announced that its new Nova application processors will include Imagination’s next-generation PowerVR Series6 ‘Rogue’ architecture.[7]

List of PowerVR chipsets [edit]

  • [1] Official Imgtec data
  • [2] USSE (Universal Scalable Shader Engine) pipes/TMUs
  • [3] USSE2 (Universal Scalable Shader Engine 2) pipes/TMUs
  • All models support Tile based deferred rendering (TBDR)

Series 1 [edit]

Model Launch Fab (nm) Memory (MiB) Core clock (MHz) Memory clock (MHz) Config core1 Fillrate Memory
MOperations/s MPixels/s MTextels/s MVertices/s Bandwidth (GB/s) Bus type Bus width (bit)
PCX11996500460601:0:1:160606000.48SDR64
PCX21997350466661:0:1:166666600.528SDR64

Series 2 [edit]

  • All models are fabricated with a 250 nm process
  • All models support DirectX 6.0 and the PMX1 supports MiniGL
Model Launch Memory (MiB) Core clock (MHz) Memory clock (MHz) Config core1 Fillrate Memory
MOperations/s MPixels/s MTextels/s MVertices/s Bandwidth (GB/s) Bus type Bus width (bit)
CLX2199881001001:0:1:110010010000.8SDR64
PMX11999321251251:0:1:112512512501SDR64

Series 3 [edit]

Model Launch Fab (nm) Memory (MiB) Core clock (MHz) Memory clock (MHz) Config core1 Fillrate Memory
MOperations/s MPixels/s MTextels/s MVertices/s Bandwidth (GB/s) Bus type Bus width (bit)
STG4000200025032/641151152:0:2:223023023001.84SDR128
STG4500200118032/641751752:0:2:235035035002.8SDR128
STG4800Never Released180642002002:0:2:240040040003.2SDR128
STG5500Never Released130642502504:0:4:410001000100004DDR128

Series 4 [edit]

Model Year Die Size (mm2)[1] Config core Fillrate (@ 200 MHz) Bus width (bit) API (version)
MTriangles/s[1] MPixel/s[1] DirectX OpenGL
MBX LiteFeb 20014@130 nm?0/1/1/11.0100648.01.1
MBXFeb 20018@130 nm?0/1/1/11.68150648.01.1

Series 5 [edit]

Model Year Die Size (mm2)[1] Config core[2] Fillrate (@ 200 MHz) Bus width (bit) API (version) GFLOPS(@ 200 MHz)
MTriangles/s[1] MPixel/s[1] DirectX OpenGL OpenGL ES
SGX520Jul 20052.6@65 nm1/1710064 N/A N/A2.00.8
SGX530Jul 20057.2@65 nm2/11420064 N/A N/A2.01.6
SGX531Oct 200665 nm2/11420064 N/A N/A2.01.6
SGX535Nov 200765 nm2/214400649.0c2.12.01.6
SGX540Nov 200765 nm4/22040064 N/A N/A2.03.2
SGX545Jan 201012.5@65 nm4/2404006410.13.22.03.2

Series 5XT [edit]

Model Date Cores Die Size (mm2)[1] Config core[3] Fillrate (@ 200 MHz) Bus width (bit) API (version) GFLOPS(@ 200 MHz,per core)
MTriangles/s[1] MPixel/s[1] DirectX OpenGL OpenCL
SGX543Jan 20091-165.4@32 nm4/2351000649.0 L32.11.17.2
SGX544Jun 20101-165.4@32 nm4/2351000649.0 L32.11.17.2
SGX554Dec 20101-168.7@32 nm8/2451000649.0 L32.11.114.4

These GPU can be used in either single-core or multi-core configurations.[8]

Series 6 (Rogue) [edit]

Model Date Cores Die Size (mm2) Config core[3] Fillrate (@600 MHz) Bus width (bit) API (version) GFLOPS(@600 MHz)
MPolygons/s GPixel/s DirectX OpenGL OpenGL ES
G6100Feb 20131??@28 nm1/2175??9.0 L33.x3.0 
G6200Jan 20121??@28 nm2/11752.5?10.03.x/4.x3.0 
G6230Jun 20121??@28 nm2/11752.5?10.03.x/4.x3.0 
G6400Jan 20121??@28 nm4/23505?10.03.x/4.x3.0 
G6430Jun 20121??@28 nm4/23505?10.03.x/4.x3.0 
G6630Nov 20121??@28 nm6/25257.5?10.03.x/4.x3.0 

See also [edit]

References [edit]

External links [edit]

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