FPGA学习笔记2.1——用Verilog实现74LS148的功能定义并测试

设计思路：

0－7 编码输入端(低电平有效)

EI 选通输入端(低电平有效)

A0、A1、A2 三位二进制编码输出信号即编码 输 出 端(低电平有效)

GS 片优先编码输出端即宽展端(低电平有效)

EO 选通输出端，即使能输出端

74LS148真值表：

输入									输出
EI	0	1	2	3	4	5	6	7	A2	A1	A0	GS	EO
1	X	X	X	X	X	X	X	X	1	1	1	1	1
0	1	1	1	1	1	1	1	1	1	1	1	1	0
0	X	X	X	X	X	X	X	0	0	0	0	0	1
0	X	X	X	X	X	X	0	1	0	0	1	0	1
0	X	X	X	X	X	0	1	1	0	1	0	0	1
0	X	X	X	X	0	1	1	1	0	1	1	0	1
0	X	X	X	0	1	1	1	1	1	0	0	0	1
0	X	X	0	1	1	1	1	1	1	0	1	0	1
0	X	0	1	1	1	1	1	1	1	1	0	0	1
0	0	1	1	1	1	1	1	1	1	1	1	0	1

其中，1－高电平 ，0－低电平 ，X－任意

原理图： 

功能模块代码：

module code83(in8,out3,EI,GS,EO);
input[7:0] in8;
input EI;
output reg[2:0] out3;
output reg GS;
output reg EO;
always@(in8,EI)
begin
	out3=3'b111;
	EO=1;
	GS=1;
	if(~EI)
	begin
		GS=0;
		case(in8)
			8'b11111111:

			begin
				EO=0;
				GS=1;
				out3=3'b111;
			end
			8'b00000000: out3=3'b000;
			8'b10000000: out3=3'b001;
			8'b11000000: out3=3'b010;
			8'b11100000: out3=3'b011;
			8'b11110000: out3=3'b100;
			8'b11111000: out3=3'b101;
			8'b11111100: out3=3'b110;
			8'b11111110: out3=3'b111;
			default: out3=3'b111;
		endcase
	end
end
endmodule

测试模块代码：

// Copyright (C) 2017  Intel Corporation. All rights reserved.
// Your use of Intel Corporation's design tools, logic functions 
// and other software and tools, and its AMPP partner logic 
// functions, and any output files from any of the foregoing 
// (including device programming or simulation files), and any 
// associated documentation or information are expressly subject 
// to the terms and conditions of the Intel Program License 
// Subscription Agreement, the Intel Quartus Prime License Agreement,
// the Intel FPGA IP License Agreement, or other applicable license
// agreement, including, without limitation, that your use is for
// the sole purpose of programming logic devices manufactured by
// Intel and sold by Intel or its authorized distributors.  Please
// refer to the applicable agreement for further details.

// *****************************************************************************
// This file contains a Verilog test bench template that is freely editable to  
// suit user's needs .Comments are provided in each section to help the user    
// fill out necessary details.                                                  
// *****************************************************************************
// Generated on "03/30/2022 22:16:56"
                                                                                
// Verilog Test Bench template for design : code83
// 
// Simulation tool : ModelSim-Altera (Verilog)
// 

`timescale 1 ps/ 1 ps
module code83_vlg_tst();
// constants                                           
// general purpose registers
reg eachvec;
// test vector input registers
reg EI;
reg [7:0] in8;
// wires                                               
wire EO;
wire GS;
wire [2:0]  out3;

// assign statements (if any)                          
code83 i1 (
// port map - connection between master ports and signals/registers   
	.EI(EI),
	.EO(EO),
	.GS(GS),
	.in8(in8),
	.out3(out3)
);
initial                                                
begin                                                  
// code that executes only once                        
// insert code here --> begin                          
                                                       
// --> end                                             
$display("Running testbench");    
EI=1;in8=8'b0;
#5;
EI=0;
in8=8'b11111111;
#16 $stop;   
                
end                                                    
always                                                 
// optional sensitivity list                           
// @(event1 or event2 or .... eventn)                  
begin                                                  
// code executes for every event on sensitivity list   
// insert code here --> begin      
#2 $display("EI:%b; input:%b; output:%b GS:%b; EO:%b",EI,in8,out3,GS,EO);
in8=in8<<1;                    
                                                       
@eachvec;                                              
// --> end                                             
end                                                    
endmodule

运行图：