学习日志之arm汇编遗漏基础补充

ARM processors are typical of RISC processors in that only load and store instructions can access memory. Data processing instructions operate on register contents only.

 

All ARM instructions are 32 bits long. Instructions are stored word-aligned, so the least significant two bits of instruction addresses are always zero in ARM state.

Thumb instructions are either 16 or 32 bits long. Instructions are stored half-word aligned. Some instructions use the least significant bit of the address to determine whether the code being branched to is Thumb code or ARM code.

the 32-bit and 16-bit Thumb instructions provide functionality that is almost identical to that of the ARM instruction set.

 

The processor must be in the correct instruction set state for the instructions it is executing.

• A processor that is executing ARM instructions is operating in ARM state.
• A processor that is executing Thumb instructions is operating in Thumb state.
• A processor that is executing ThumbEE instructions is operating in ThumbEE state. 
• A processor can also operate in another state called the Jazelle® state. The assembler cannot directly assemble code for the Jazelle state.

The initial state after reset depends on the processor being used and its configuration.

to direct the assembler to generate ARM or Thumb instruction encodings, you must set the assembler mode using an ARM or THUMB directive. To generate ThumbEE code, use the THUMBX directive

 

The processor modes available in ARMv6-M and ARMv7-M are Thread mode and Handler mode.

• Thread mode is the normal mode that programs run in. Thread mode can be privileged or unprivileged software execution
• Handler mode is the mode that exceptions are handled in. It is always privileged software execution.

 

In all ARM processors, the following registers are available and accessible in any processor mode:

• 13 general-purpose registers R0-R12.
• One Stack Pointer (SP).
• One Link Register (LR).
• One Program Counter (PC).
• One Application Program Status Register (APSR).

 

The Link Register can also be used as a general-purpose register. The Stack Pointer can be used as a general-purpose register in ARM state only.

 

• Most 16-bit Thumb instructions can only access R0 to R7. Only a small number of these instructions can access R8-R12, SP, LR, and PC. Registers R0 to R7 are called Lo registers. Registers R8-R12, SP, LR, and PC are called Hi registers.
• All 32-bit Thumb instructions can access R0 to R12, and LR. However, apart from a few designated stack manipulation instructions, most Thumb instructions cannot use SP. Except for a few specific instructions where PC is useful, most Thumb instructions cannot use PC.
• In ARM state, all instructions can access R0 to R12, SP, and LR, and most instructions can also access PC (R15). However, the use of the SP in an ARM instruction, in any way that is not possible in the corresponding Thumb instruction, is deprecated. Explicit use of the PC in an ARM instruction is not usually useful, and except for specific instances that are useful, such use is deprecated. Implicit use of the PC, for example in branch instructions or load (literal) instructions, is never deprecated

 

You must write instruction mnemonics, pseudo-instructions, directives, and symbolic register names (except a1-a4, v1-v8, and Wireless MMX registers) in either all uppercase or all lowercase. You must not use mixed case. Labels and comments can be in uppercase, lowercase, or mixed case.

To make source files easier to read, you can split a long line of source into several lines by placing a backslash character (\) at the end of the line. The backslash must not be followed by any other characters, including spaces and tabs

 

Use the AREA directive to name the section and set its attributes. The attributes are placed after the name, separated by commas.