verilog写12 小时时钟（带上午/下午指示器）计数器(HDLbits Count clock)

最新推荐文章于 2024-07-19 17:42:39 发布

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最新推荐文章于 2024-07-19 17:42:39 发布

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文章标签： fpga开发

本文链接：https://blog.csdn.net/zcy000810/article/details/139838691

版权

Create a set of counters suitable for use as a 12-hour clock (with am/pm indicator). Your counters are clocked by a fast-running clk, with a pulse on ena whenever your clock should increment (i.e., once per second).

reset resets the clock to 12:00 AM. pm is 0 for AM and 1 for PM. hh, mm, and ss are two BCD (Binary-Coded Decimal) digits each for hours (01-12), minutes (00-59), and seconds (00-59). Reset has higher priority than enable, and can occur even when not enabled.

The following timing diagram shows the rollover behaviour from 11:59:59 AM to 12:00:00 PM and the synchronous reset and enable behaviour.

比较蠢的方法，无限if嵌套，对着波形改了好久

module top_module(
    input clk,
    input reset,
    input ena,
    output pm,
    output [7:0] hh,
    output [7:0] mm,
    output [7:0] ss); 
    reg [7:0] hh1,mm1,ss1;
    always@(posedge clk)
        begin
        if(reset)
            begin
                ss<=0;
                hh<=8'b00010010;
                mm<=0;
            end
       else if(ena)
                begin
                    if((hh == 8'h11)&&(mm == 8'h59)&&(ss == 8'h59))
                        pm<=~pm;
                    else
                        pm<=pm;
                    if(ss[3:0]==4'd9)
                        begin
                            ss[3:0]<=0;
                            if(ss[7:4]==4'd5&&ss[3:0]==4'd9)
                                begin
                                    ss<=0;
                                    if(mm[3:0]==4'd9)
                                        begin
                                            mm[3:0]<=0;
                                            if(mm[7:4]==4'd5&&mm[3:0]==4'd9)
                                                 begin
                                                     mm<=0;
                                                     if(hh[3:0]==4'd9)
                                                         begin
                                                             hh[3:0]<=4'b0;
                                                             hh[7:4]<=1;
                                                         end
                                                     else if(hh[7:4]==4'd1&&hh[3:0]==4'd2)
                                                           hh<=1;
                                                     else
                                                         hh[3:0]<=hh[3:0]+1'b1;
                                                 end
                                            else
                                                mm[7:4]<=mm[7:4]+1'b1;
                                        end
                                    else
                                        mm[3:0]<=mm[3:0]+1'b1;
                                end
                            else
                                ss[7:4]<=ss[7:4]+1'b1;
                        end
                    else
                        ss[3:0]<=ss[3:0]+1'b1;
                end            
        end
endmodule