FPGA architecture overview

 programming technology:

• static memory (RAM): main stream methodology. the SRAM used for:
  1. programming the routing interconnects that are usually steered by small multiplexors
  2. programming CLBs that are used to implement logic functions
  3. volatile
• flash (EEPROM): 
  1. nonvolatile in nature
  2. area efficient than SRAM
  3. but can not be reconfigured/reprogrammed an infinite number of times
  4. non-standard CMOS process
• anti-fuse:
  1. lower area and lower on resistance and parasitic cap than the other two
  2. non-volatile in nature
  3. non standard CMOS
  4. cannot be re-programmed

CLB (configurable logic block):

• basic logic + storage capability
• commercial vendors use LUT based CLB instead of NAND gates, PAL, etc
• CLB comprises of clusters of basic logic elements (BLE)
• BLE = LUT + Flip-Flop, LUT-k means k-input boolean functions. example: LUT-4 uses 16 SRAM bits to implement any 4 inputs boolean function.

• between the BLEs within a cluster, the communication is through a local routing network. modern FPGA typically contains 4 to 10 BLEs in a single cluster.
• besider CLB (BLE), modern FPGA contains a heterogeneous mixture of blocks, some of which are for spcific purpose, referred as hard blocks, include memory, multipliers, adders, and DSP blocks.

FPGA routing architecture:

• programmable routing network: provide connections among logic blocks, IO blocks; consists of wires and programmable switches that form the requried connection and configured using the prgrammable technology.
• most design exhibit locality, hence requiring abundant short wires, but still there are times for distant connections. the arrangement of routing resources, relative to the arrangement of logic blocks, plays a very impor