ICC实验-基于2010年Synopsy的lab guide
文章目录
- ICC实验-基于2010年Synopsy的lab guide
- 1 ICC实验
- 1.1 Intro to ICC
- 1.2 Data_Setup
- 1.3 Design_Planning
- Task 1 Load the Design
- Task 2 Initialize the Floorplan
- Task 3 Preplace the Macros Connected to IO Pads
- Task 4 Perform Virtual Flat Placement
- Task 5 Create PG Rings Around Macro Groups
- Task 6 Power Network Synthesis
- Task 7 Check the Timing
- Task 8 Write out the DEF Floorplan File
- Task 9 Create 2nd Pass Design Ready for Placement
- 1.4 Placement
- 1.5 CTS
1 ICC实验
在readme里可以看到,用的是ICC_201012实验,而不是2007
实验链接如下,或者点此处跳转
https://download.csdn.net/download/Zhong_ty/87658647
1.1 Intro to ICC
Begin
启动icc(IC compiler)
icc_shell
icc_shell>start_gui
或者直接
icc_shell -gui
open design -> select library -> .mw
Milkway是对synopsys的Milkway数据格式进行管理的软件。对于后端而言,使用ICC做设计时,厂家会提供一个完整的标准单元库的Milkyway库,但是如果你的design里面有IP等,你可能只有一个lef或GDS文件,这时候就需要用Milkway软件把这些转化成ICC可以处理的Milkway库。
Milkway相当于一个盒子,装了所有跟设计相关的数据,不管是工艺厂的,还是自己的设计数据。
打开之后,如下图所示,并观察
Q(select->query selection):开query tool
ctrl+r:看properties
Analyze Timing Paths
“Path Slack”:之后reload一下->OK
会显示多个路径,其中紫色的slack最小,时序最紧,之后是红色
选中紫色路径下的模块(IO PAD),在Main window下可以查看选中的模块所处的schematic
通过双击或者右键->Next Fanin/Fanout Level很出现与其相连的模块。
如果想看整个电路,右键->add logic->paths…。如果什么都不选中(ctrl+d),通过schematic->new design schematic view,可以看到整个电路图
overall timing quality 测量:
在mainwindow中window->new timing analysis window
点击不同的线路,在schematic中以及layout中也会相应显示出来
下方的这三个功能分别对应显示所有stack的直方图,显示path的一些数据以及显示schematic
可以通过ctrl+`切换界面
1.2 Data_Setup
Task 1 Create a Milkyway library
首先在.synopsys_dc.setup文件里可以看到有一些预先设置好的变量,以及logic library如下
并通过icc_shell>printvar sdc_file查看setup是否正确被写进(输出是否和上面set sdc_file一致)
create the design library
mainwindow->file->create library->填信息(根据上面在.setup里看到的)其中的input reference libraries都在ref文件夹中。这是log里会有warning,找不到CapMpdel,先忽略,后面会fix
可以看到milkway library创建成功
Task 2 Load the Netlisg, TLU+,Constraints and Controls
导入verilog:MainWindow->File->Open Library
导入TLU+
TLUPlus是存储RC系数的二进制表格式。 TLUPlus模型通过包括宽度,空间,密度和温度对电阻系数的影响,可以实现精确的RC提取结果。
MainWindow->File->Set TLU±>配置
简单check一下配置:check_library
其中missing in logic library有19个,misiing or mismatched pins有12个。这些知识因为名称不一样导致,可以忽略
check_tlu_plus_files,tlu+库对完整性(sanity)check也pass
list_libs:检查link library
通过source $derive_pg_file定义logical连接,并用check_mv_design -power_nets检查,下面为source前后的check
apply constraints:
- read_sdc $sdc_file
check一下:无warning和error即可
-
check_timing
-
report_timing_requirments:是否有时间异常,包括错误的path和多循环的path
-
report_disable_timing:检查是否在任何路径上禁用了时序分析
-
report_case_analysis:检查设计是否已配置为特定的“mode”或“case”
-
report_clock: 8 time unit {0 4}
-
report_clock -skew
apply controls:
- source $ctrl_file
remove ideal的信号:remove_ideal_network [get_ports scan_en]
save milkway:
- save_mw_cel –as RISC_CHIP_data_setup
Task 3 Basic Flow : Design Planning
这里已经给了floorplan,在标准格式DEF中,这个file可以被icc生成
首先read_def $def_file或者file->import->read def,to read
这时候再看layout窗口如下:floorplan已经生成
为了确保标准单元不会被placed在power和gnd金属层布线,需要:
set_pnet_options -complete {METAL3 METAL4}
save design cell:(floorplan过的)保存的文件会在.mw文件夹下的CEL文件夹
save_mw_cel –as RISC_CHIP_floorplanned
Task 4 Basic Flow : Placement
首先place和optimize timing设计,并生成timing报告
place_opt
redirect -tee place_opt.timing {report_timing}
#无报错
Analyze congestion in layout
Global Route Congestion->reload
Save the design cell:
save_mw_cel –as RISC_CHIP_placed
此时的layout如下
Task 5 Basic Flow : CTS
Clock tree synthesis
remove_clock_uncertainty [all_clocks]
set_fix_hold [all_clocks]
clock_opt
redirect -tee clock_opt.timing {report_timing}
clock_opt后的layout如下图
display clock tree:可以显示出来clock tree的走向,从clk_iopad到core
LayoutWindow->clock->color by clock trees->reload->all level,types->OK
save一下之后route一下
如果重新打开design,需要重新应用一下controls,之后route opt
source $ctrl_file
route_opt
route_opt后的layout如下(局部放大)
生成timing report
-
view report_timing -nosplit
-
view report_timing -delay min
生成physical design 信息
- report_design –physical
例如会report金属层的连线长度
1.3 Design_Planning
Task 1 Load the Design
open orca_setup in orca_lib.mw,此时的layout如下
apply timing and optimization controls:
source scripts/opt_ctrl.tcl
之后在layout中点开file->task->design planning
Task 2 Initialize the Floorplan
建立 corner P/G pad 的位置:
先检查cell都被created了并且没错
source –echo scripts/pad_cell_cons.tcl
Initialize the floorplan:
Floorplan->initialize floorplan->修改设定
可以看到上方还有大量的离散的蓝色矩形,这些都是未放置的宏单元格,每个pad到中间core的距离都是30.右边的紫色都是标准单元
填补pads之间的gap,可能需要n-wll或者p-well对于power还是gnd,需要提前规定填充的filler 的大小,并进行填充
source scripts/insert_pad_filler.tcl
#or
insert_pad_filler –cell "pfeed10000 pfeed05000 \
pfeed02000 pfeed01000 pfeed00500 pfeed00200 \
pfeed00100 pfeed00050 pfeed00010 pfeed00005"
放大观察pad之间如下所示
对power/ground信号和所有pin,IOpad,Macros以及标准单元进行“logical”相连 而不是物理上的布线,此时layout上并没有变化
source –echo scripts/connect_pg.tcl
Build the PAD area power supply ring:
create_pad_rings
可以看到pad上已经形成了电流网络
save一下
save_mw_cel –as floorplan_init
Task 3 Preplace the Macros Connected to IO Pads
Identify macros that connect to I/O pads:
Select->cells->by types->进行选择。之后可以看到在版图中对应的macor已经被选中
然后选择Flylines ,选择只看macro到io的飞线。发现只有3个macro需要连接到 IOpad上
首先选择I_PLL_PCI macro,他是连在左边的pad上的,可以通过align功能进行对齐,并且通过padlock将该模块固定。这里可以不用担心,place macro的时候位置太差,之后会有script可以运行
将剩余两个macro摆放好,如下图所示
为了确保放的正确,运行下列代码去进行放置
source –echo scripts/preplace_macros.tcl
Task 4 Perform Virtual Flat Placement
Verify that the current VF placement strategy options have default settings:
report_fp_placement_strategy
可以看到现在默认的sliver size距离是0.00
Apply a sliver size of 10 to prevent standard cells from being placed in narrow channels (< 10 um) between macros:
set_fp_placement_strategy -sliver_size 10
改变后
执行一个时间驱动的VF placement且没有hierarchy gravity来保证logical
hierarchy不影响非层次的layout
create_fp_placement –timing_driven –no_hierarchy_gravity
测一下global route congestion map,点Global Route Congestion->Reload
这时会报error,显示是macro没有fixed,这个可以忽略,后面script会fixed掉
source –echo scripts/macro_place_cons.tcl
check setting
report_fp_placement_strategy
report_fp_macro_options
运行下面的tcl,留10 microns 的hard keepout margin 。这保证PG rings创建的更简单以及避免信号通路drc报错
source –echo scripts/keepout.tcl
然后再重新run一次VF placer
create_fp_placement –timing_driven –no_hierarchy_gravity
这时在看layout,变得不一样,已经形成了grouping,布局更加合理
Analyze the global route congestion map again:
这时不会再有congestion问题
把所有的macros lock down,所有的macro都被锁定了
set_dont_touch_placement [all_macro_cells]
然后保存
Task 5 Create PG Rings Around Macro Groups
运行脚本去生成PG rings
source ./scripts/macro_pg_rings.tcl
生成的layout如下所示
Task 6 Power Network Synthesis
用ICC的Power Network Synthesis,PNS,基于一个目标IRdrop去自动确定straps的数目以及宽度以及core ring的宽度
appky strap constraints
Preroute->Power Network Constraints->Strap Layers Constraints…
apply core ring constraint:
Preroute->Power Network Constraints->Ring Constraints…
Define a macro ring for the PLL macro without a ring:
Preroute->Power Network Constraints->Block Rings Constraints…
Apply global constraints:
Preroute->Power Network Constraints->Global Constraints…
invoke PNS:
Preroute->Synthesize Power Network…
为了完成PG的连接,要把power pin 连到所有的macros上
preroute_instances
preroute_standard_cells –fill_empty_rows -remove_floating_pieces
Task 7 Check the Timing
放置以及验证最大延迟设定
PNS在金属45层上放了很多straps
set_pnet_options -complete "METAL4 METAL5"
#pnet:power net
create_fp_placement –timing_driven –no_hierarchy_gravity
Since we are about to check timing, perform actual global routing by running the following command(这语句容易直接把icc跑爆)
route_zrt_global
生成report:
v report_timing
To fix any timing violations (and design rule violations),if need
optimize_fp_timing –fix_design_rule
save as floorplan_complete.
Task 8 Write out the DEF Floorplan File
删除所有的标准单元,写.def格式文件
remove_placement -object_type standard_cell
write_def –version 5.6 –placed –all_vias –blockages \
-routed_nets –rows_tracks_gcells –specialnets \
–output design_data/ORCA.def
然后不用保存当前的版图,直接退出
Task 9 Create 2nd Pass Design Ready for Placement
Perform data setup using the new ORCA netlist and constraints
source scripts/2nd_pass_setup.tcl
这个脚本运行了包括create mw_lib,import design,set tlu+,connect_pg,opt_ctrl等命令
read def file:
read_def design_data/ORCA.def
1.4 Placement
Task 1 Pre-placement Settings and Checks
open library以及design cell
apply timing and optimization controls
source scripts/opt_ctrl.tcl
It is therefore a good idea to repeat the “fixing” step prior to placement to ensure that no macros are moved during the placement phase:
set_dont_touch_placement [all_macro_cells]
verify that all process metal layers are available for routing ,结果显示都可以用
report_ignored_layers
Verify that standard cells are allowed to be placed under the METAL2 –METAL4 power nets,同时没有drc报错
report_pnet_options
During design planning both soft and hard placement keepouts were applied. Verify that these variables are still set and are not the default value of zero:分别是5,15
printvar physopt_hard_keepout_distance
printvar placer_soft_keepout_channel_width
Apply the non-default routing rules for all clock nets
Source scripts/ndr.tcl
Verify that the floorplanned design is ready for placement:无报错
check_physical_design –stage pre_place_opt
check 约束
check_physical_constraints
Execute the following command to confirm that no scan chain information exists:一共存在11个扫描链
report_scan_chain
#or
v report_scan_chain
改变simulator-generated
report_saif
source scripts/inputs_toggle_rate.tcl
report_saif
check功耗选项,只开了泄露功耗的优化,还需要把low_power_placement打开
report_power_options
set_power_options –low_power_placement true
save as ORCA_preplace_setup
Task 2 Placement and Optimization
进行place 的opt,针对power
place_opt –area_recovery -optimize_dft -power
save as ORCA_place_opt
查看global Route Congestion,不是很多,比较离散
report_design -physical
可以看到标准单元用了81%.
#看setup time的violation
report_qor
#功耗
report_power
Task 3 Incremental Optimization
开启动态功耗优化
set_power_options –dynamic true
perform incremental logic optimization, using appropriate options:
psynopt -area_recovery –power
看一下前后功耗。优化后是总动态功耗为33mW,cell的泄露功耗为421uW
save as ORCA_placed
1.5 CTS
Task 1 Copy and Load the Working CEL
打开mw文件,并copy一份文件place_opt到clock_opt,并打开
copy_mw_cel –from place_opt –to clock_opt
Task 2 Examine the Clock Trees
report clk的一些属性。clk最小uncertainty为SD_DDR_CLK 0.05ns
report_clock –skew -attributes
report_clock_tree -summary
view report_constraint -all
打开InteractiveCTSWindow
可以点击 Show clock tree browser of selected clock进行进一步分析
在sdram_clk中可以看到18个pins被分为了“implicit_exclude_pin”这是因为这些引脚是SELECT引脚
mux。这些引脚将被忽略时钟树倾斜和延迟优化。
Task 3 Preparing for Clock Tree Synthesis
修改上一小节中的implicit_exclude_pin为stop_pin
set_clock_tree_exceptions -stop_pins {I_SDRANM_TOP/I_SDRAM_IF/sd_mux_*/S}
把clk skew设置为0.1,对于所有的clocks。让所有的uncertainty为0.1。给CTS指定buffers
set_clock_tree_options -target_skew 0.1
set_clock_uncertainty 0.1 [all_clocks]
set_clock_tree_references -references {bufbd1 bufbd2 bufbd4 bufbd7 bufbdf}
Configure CTS to use non-default routing
define_routing_rule CLOCK_DOUBLE_SPACING -spacings {METAL3 0.42 METAL4 0.6 METAL5 0.82}
report一下
report_routing_rule CLOCK_DOUBLE_SPACING
直接CTS在所有时钟路由上使用CLOCK_DOUBLE_SPACING NDRs,除了level1(还是用默认的).,同时限制时钟通路在M3-M5
set_clock_tree_options -routing_rule CLOCK_DOUBLE_SPACING -layer_list{METAL3 METAL5} -use_default_routing_for_sinks 1
report 一下
v report_clock_tree -settings
在运行CTS之前,check一下,但是没有网络就无法打开界面
check_physical_design –stage pre_clock_opt -display
将时钟延迟计算器设置为Arnoldi。这让延迟计算采用更精确的Arnoldi-based的时钟网时延模型
CTS设计(取代默认的基于elmore的延迟模型)
set_delay_calculation –clock_arnoldi
check
check_clock_tree
Task 4 Perform Clock Tree Synthesis
首先在没有opt的情况下进行生成
clock_opt –only_cts –no_clock_route
report一下
report_clock_tree -summary
通过下面report
report_clock_timing -type skew –significant_digits 3
发现两个report的数值不同。这是因为
The report_clock_tree command reports “global”skew:meaning the maximum skew across the entire clock domain 。 Furthermore, report_clock_tree does not take into account any timing derating (set_timing_derate).
The second report calculates actual (or “local”) clock skew:The reported maximum skew is between two flip flops of that clock domain that share a timing path (one clock branch launches the data while the other branch captures the data).
save as clock_opt_cts
Task 5 Perform Hold Time Optimization
Enable hold time fixing
set_fix_hold [all_clocks]
report_qor看design area为80398.
use the area critical range setting,这回减小crosstalk
et_max_area 0 ;# This is already set previously
set physopt_area_critical_range 0.2
确保当前RC提取数据是可以捕获到更准确的“integrated clock global router” (ICGR)
extract_rc
执行post-CTS timing,area ,scan chain OPT,在没有clok routing的前提下
clock_opt –only_psyn -area_recovery –optimize_dft –no_clock_route
report一下
report_qor
report_constraint -all
save as clock_opt_psyn
Task 6 Route the Clocks
Route时钟
route_zrt_group -all_clock_nets -reuse_existing_global_route true
分析constraints,保证没有drc或者timing的违反
report_constraint -all
在layout里把cell,power,ground先隐藏,可以看到clk都在M3 M4 M5
分析时钟网络级拓扑结构。选择clock trees->reload