PCIe系列专题之三:3.0 数据链路层概述

一、故事前传

之前我们讲了对PCIe的一些基础概念作了一个宏观的介绍,了解了PCIe是一种封装分层协议(packet-based layered protocol),主要包括事务层(Transaction layer), 数据链路层(Data link layer)和物理层(Physical layer)。

较为详细解释请见之前的文章:

1. PCIe技术概述;

2.0~2.8 PCIe Transaction layer事务层详细解析;

二、数据链路层概述

之前的文章中,我们提到"在PCIe体系结构中,数据报文首先在设备的核心层(Device Core)中产生,然后再经过该设备的事务层(Transaction Layer)、数据链路层(Data Link Layer)和物理层(Physical Layer),最终发送出去。而接收端的数据也需要通过物理层、数据链路和事务层,并最终到达Device Core。"

从上图中,我们也可以明显的看到,Data Link Layer在PCIe总线中处于承上启下的作用,保证来自事务层的TLPs在PCIe总线中正常的传递。

  • 在发送端,当Transaction Layer事务层的TLPs传进来时,Data Link Layer会在TLP前后两端分别加上Sequence以及LCRC部分。

  • 在接收端,数据链路层接收到TLP报文之后进行拆解,剥离Sequence和LCRC部分,再传送至事务层。

此外,数据链路层使用了Retry与监控机制(Ack/Nak)来保证数据传输的一致性和完整性。

来自事务层的TLPs,再加上前缀Sequence和后缀LCRC之后,会首先暂存在数据链路层的TLP Retry Buffer,然后再发送至接收端。发送端会根据接收端传到的Ack/Nak DLLP决定是否需要重新发送TLP。如果不需要重新发送,则将其从TLP Retry Buffer里清除。

注意: DLLP不同于TLP,是产生与数据链路层,中止与数据链路层。DLLP并不是有TLP加上Sequence和LCRC组成的,具有单独的格式。

后续会对数据链路层的DLLP结构以及Ack/Nak进行详细的介绍,敬请期待!谢谢! 

Contents OBJECTIVE OF THE SPECIFICATION............................................................................... 23 DOCUMENT ORGANIZATION.............................................................................................. 23 DOCUMENTATION CONVENTIONS................................................................................... 24 TERMS AND ACRONYMS ...................................................................................................... 25 REFERENCE DOCUMENTS................................................................................................... 32 1. INTRODUCTION............................................................................................................... 33 1.1. A THIRD GENERATION I/O INTERCONNECT ................................................................... 33 1.2. PCI EXPRESS LINK......................................................................................................... 35 1.3. PCI EXPRESS FABRIC TOPOLOGY .................................................................................. 37 1.3.1. Root Complex........................................................................................................ 37 1.3.2. Endpoints .............................................................................................................. 38 1.3.3. Switch.................................................................................................................... 41 1.3.4. Root Complex Event Collector.............................................................................. 42 1.3.5. PCI Express to PCI/PCI-X Bridge........................................................................ 42 1.4. PCI EXPRESS FABRIC TOPOLOGY CONFIGURATION ....................................................... 42 1.5. PCI EXPRESS LAYERING OVERVIEW........................................................................
OBJECTIVE OF THE SPECIFICATION.................................................................................... 27 DOCUMENT ORGANIZATION ................................................................................................ 27 DOCUMENTATION CONVENTIONS...................................................................................... 28 TERMS AND ACRONYMS........................................................................................................ 29 REFERENCE DOCUMENTS...................................................................................................... 36 1. INTRODUCTION ................................................................................................................ 37 1.1. A THIRD GENERATION I/O INTERCONNECT ................................................................... 37 1.2. PCI EXPRESS LINK......................................................................................................... 39 1.3. PCI EXPRESS FABRIC TOPOLOGY .................................................................................. 41 1.3.1. Root Complex........................................................................................................ 41 1.3.2. Endpoints .............................................................................................................. 42 1.3.3. Switch.................................................................................................................... 45 1.3.4. Root Complex Event Collector.............................................................................. 46 1.3.5. PCI Express to PCI/PCI-X Bridge........................................................................ 46 1.4. PCI EXPRESS FABRIC TOPOLOGY CONFIGURATION....................................................... 46 1.5. PCI EXPRESS LAYERING OVERVIEW.............................................................................. 47 1.5.1. Transaction Layer................................................................................................. 48 1.5.2. Data Link Layer .................................................................................................... 48 1.5.3. Physical Layer ...................................................................................................... 49 1.5.4. Layer Functions and Services............................................................................... 49 2. TRANSACTION LAYER SPECIFICATION ..................................................................... 53 2.1. TRANSACTION LAYER OVERVIEW.................................................................................. 53 2.1.1. Address Spaces, Transaction Types, and Usage................................................... 54 2.1.2. Packet Format Overview ...................................................................................... 56 2.2. TRANSACTION LAYER PROTOCOL - PACKET DEFINITION............................................... 58 2.2.1. Common Packet Header Fields ............................................................................ 58 2.2.2. TLPs with Data Payloads - Rules ......................................................................... 61 2.2.3. TLP Digest Rules .................................................................................................. 65 2.2.4. Routing and Addressing Rules .............................................................................. 65 2.2.5. First/Last DW Byte Enables Rules........................................................................ 69 2.2.6. Transaction Descriptor......................................................................................... 71 2.2.7. Memory, I/O, and Configuration Request Rules................................................... 77 2.2.8. Message Request Rules......................................................................................... 83 2.2.9. Completion Rules.................................................................................................. 97 2.2.10. TLP Prefix Rules ................................................................................................. 100 2.3. HANDLING OF RECEIVED TLPS.................................................................................... 104
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