练习七 在Verilog HDL中使用task任务

源代码

`timescale 1ns / 1ps
//
// Company: 
// Engineer: 
// 
// Create Date:    11:17:58 07/27/2019 
// Design Name: 
// Module Name:    sort4_test 
// Project Name: 
// Target Devices: 
// Tool versions: 
// Description: 
//
// Dependencies: 
//
// Revision: 
// Revision 0.01 - File Created
// Additional Comments: 
//
//
module sort4_test(
						ra,
						rb,
						rc,
						rd,
						a,
						b,
						c,
						d
    );
	output [3:0]ra,rb,rc,rd;
	input [3:0]a,b,c,d;
	reg [3:0]ra,rb,rc,rd;
	reg [3:0]va,vb,vc,vd;

	always @(a or b or c or d)
		begin
			{va,vb,vc,vd} = {a,b,c,d};
			//sort2(va,vb);
			//sort2(vb,vc);
			//sort2(vc,vd);
			//sort2(va,vb);
			//sort2(vb,vc);
			//sort2(va,vb);
			//两两比较，是否有更好的方法,上面的冒泡不如下面的
			sort2(va,vc);
			sort2(vb,vd);
			sort2(va,vb);
			sort2(vc,vd);
			sort2(vb,vc);## 标题
			{ra,rb,rc,rd} = {va,vb,vc,vd};
		end
	
	task sort2;
		inout [3:0]x,y;
		reg [3:0]tmp;
		if(x > y)
			begin
				tmp = x;			//使用阻塞性赋值，顺序执行
				x = y;
				y = tmp;
			end
	endtask

endmodule

测试代码

`timescale 1ns / 100ps


// Company: 
// Engineer:
//
// Create Date:   11:42:36 07/27/2019
// Design Name:   sort4_test
// Module Name:   D:/FPGA/project/sort4_test/testbench/vtf_sort4_test.v
// Project Name:  sort4_test
// Target Device:  
// Tool versions:  
// Description: 
//
// Verilog Test Fixture created by ISE for module: sort4_test
//
// Dependencies:
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 


module vtf_sort4_test;

	// Inputs
	reg [3:0] a;
	reg [3:0] b;
	reg [3:0] c;
	reg [3:0] d;

	// Outputs
	wire [3:0] ra;
	wire [3:0] rb;
	wire [3:0] rc;
	wire [3:0] rd;

	// Instantiate the Unit Under Test (UUT)
	sort4_test uut (
		.ra(ra), 
		.rb(rb), 
		.rc(rc), 
		.rd(rd), 
		.a(a), 
		.b(b), 
		.c(c), 
		.d(d)
	);

	initial begin
		// Initialize Inputs
		a = 0;
		b = 0;
		c = 0;
		d = 0;
		repeat(50)
			begin
				#100	a = {$random}%15;
						b = {$random}%15;
						c = {$random}%15;
						d = {$random}%15;
			end
		#100	$stop;
	end
	
      
endmodule

仿真波形