vivado下的命令行仿真

1.export simulation files

导出仿真脚本（vivado下，file>export>simulation），target simulator可选vivado simulator， modelsim，questasim，Riviera_pro等。导出的文件夹xsim 下，有对应的仿真脚本，可以作为参考。

2.vivado tcl console 下，改变路径：

pwd
cd  工程路径

如果路径不对，命令就会一直报错

3. xvlog

xvlog --relax -prj vlog.prj

The xvlog command parses the Verilog source file(s) and stores the parsed dump into a HDL library on disk

xvlog example：

    xvlog file1.v file2.v
    xvlog -work worklib file1.v file2.v
    xvlog -prj files.prj

4.xelab

 xelab --relax --debug typical --mt auto -L blk_mem_gen_v8_4_2 -L xil_defaultlib -L axi_infrastructure_v1_1_0 -L axi_register_slice_v2_1_18 -L unisims_ver -L unimacro_ver -L secureip -L xpm --snapshot board xil_defaultlib.board xil_defaultlib.glbl -log elaborate.log

对代码进行编译和解析，最后生成可执行文件，如果设计中包含ip核，我们就要同时指定glbl为顶层模块，利用-s参数生成一个snapshot文件，即仿真阶段的可执行文件

xelab Examples
    xelab work.top1 work.top2 -s cpusim
    xelab lib1.top1 lib2.top2 -s fftsim
    xelab work.top1 work.top2 -prj files.prj -s pciesim
    xelab lib1.top1 lib2.top2 -prj files.prj -s ethernetsim

5.xsim

xsim board -testplusarg TESTNAME=sample_smoke_test0 -key {Behavioral:sim_1:Functional:board} -tclbatch cmd.tcl -protoinst "protoinst_files/axi_interconnect.protoinst" -log simulate.log

其中cmd.tcl 如下：

set curr_wave [current_wave_config]
if { [string length $curr_wave] == 0 } {
  if { [llength [get_objects]] > 0} {
    add_wave /
    set_property needs_save false [current_wave_config]
  } else {
     send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console."
  }
}

run -all
quit
 

The xsim command loads a simulation snapshot to effect a batch mode simulation or provides a workspace (GUI) and/or a Tcl-based interactive simulation environment

cd D:/Vivado_projects/pcie_mac_top/xsim

xvlog --relax -prj vlog.prj

xelab --relax --debug typical --mt auto -L blk_mem_gen_v8_4_2 -L xil_defaultlib -L axi_infrastructure_v1_1_0 -L axi_register_slice_v2_1_18 -L unisims_ver -L unimacro_ver -L secureip -L xpm --snapshot board xil_defaultlib.board xil_defaultlib.glbl -log elaborate.log

xsim board -testplusarg TESTNAME=sample_smoke_test0 -key {Behavioral:sim_1:Functional:board} -tclbatch cmd.tcl -protoinst "protoinst_files/axi_interconnect.protoinst" -log simulate.log

 

文章参考《ug900-vivado-logic-simulation.pdf》