Verilog中计数器的2中写法对比

功能是，计数记到24，清零，重新计数….

第一种写法：

module   count_debug        (

                                     clk,

                                     rst_n,

                                     dout

                                     );

input                    clk;

input                    rst_n;

output         [4:0]  dout;

reg              [4:0]  cnt;

always @(posedgeclk or negedge rst_n) begin

         if(rst_n == 1'b0) begin

                   cnt <= {5{1'b0}};

         end else if(cnt == 5'd24)begin

                   cnt <= {5{1'b0}};

         end else begin

                   cnt <= cnt + 1'b1;

         end

end

assign                  dout = cnt;

endmodule

         这种写法是我常用的方式，现在来看看消耗的逻辑单元

<