注:来自网络资源
1、半加器和全加器
半加器:
S=A+B
CO=AB
全加器:
S=A+B+Cin
CO=AB+(A+B)Cin
2、实现与仿真
1)设定ModelSim的位置:Tools-Options-ModelSim
2)New project:Cyclone IV、FBGA、484pin、速度6/7/8、EP4CE15C8N、ModelSim+verilog HDL;
3、输入方法
1)原理图输入
File-New-Block Diagram/Schematic File;
双击打开SYMBOL,选择Library-primtives-logic-and2+input+output,连线;
2)IP核输入
双击打开SYMBOL,MegaWizard Plug-in Manager...
在Arithmetic中选择LPM-ADD-SUB的IP核,bits=1,unsigned,carry input/output,pipeLine,AHDL include file+instantiation template file,Generate Pins for symbol ports;
3)文本输入
File-New-Design Files-VHDL File;
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity h_add_vhd is
port
(
A:in std_logic;
B:in std_logic;
S:out std_logic;
CO:out std_logic
);
end entity;
architecture rtl of h_add_vhd is
begic
S<=A xor B;
CO <= A and B;
end rtl;
3、编译与管脚
1)set as Top-Level Entity
.pdf为工程文件+.bdf为原理图文件+.vhd为VHDL文件
全编译与进展情况Compile Design:Analysis & Synthesis + Fitter(Place & Route) + Assenbler + TimeQuest Timing Analysis +EDA Netlist Writer
2)查看编译信息
Family + Device + Total Logic elements(combinational function + logic registers) + registers + pins + memory bits + Embedded Multiplier 9-bit elements + PLL
3)查看寄存器传输级视图
Locate-locate in RTL Viewer
4)查看技术映射视图
Locate-locate in Technology Map Viewer(Post-Mapping)
Tools-Netlist Viewers-Technology Map Viewer(Post-Fitting)