--/***************************************
--** THIS FILE FOR ADC_TLC2543 MODULE
--** 有限状态机练习
--** BY YANGHUIDONG
--** DATE 20.1.2015
--***************************************/
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
ENTITY Full_FIR IS
PORT(
RST:IN STD_LOGIC;
Full_FIR:IN STD_LOGIC;
CLK:IN STD_LOGIC;
TLC2543_CLK:OUT STD_LOGIC;
TLC2543_CS:OUT STD_LOGIC;
TLC2543_OUT:OUT STD_LOGIC;
--TLC2543_DATA_OUT:OUT STD_LOGIC_VECTOR(11 DOWNTO 0);
TLC2543_IN:STD_LOGIC
);
END Full_FIR;
ARCHITECTURE ONE OF Full_FIR IS
--AD SIGNAL
SIGNAL CNT:INTEGER RANGE 0 TO 24;
SIGNAL CLK1:STD_LOGIC;
SIGNAL TLC2543_ADDRESS:STD_LOGIC_VECTOR(15 DOWNTO 0);
SIGNAL TLC2543_TMP_DATA:STD_LOGIC_VECTOR(16 DOWNTO 0);
SIGNAL TLC2543_DATA_OUT:STD_LOGIC_VECTOR(11 DOWNTO 0);
BEGIN
--**********************************************
--AD Module
--分频进程
U1:PROCESS(CLK,RST)
BEGIN
IF RST='0' THEN
CNT<=0;
CLK1<='1';
ELSIF CLK'EVENT AND CLK='1' THEN
IF CNT=10 THEN
CNT<=0;
CLK1<= NOT CLK1;
ELSE
CNT<=CNT+1;
END IF;
END IF;
END PROCESS U1;
--ADC
U2:PROCESS(RST,CLK1)
VARIABLE NEXT_STATE:INTEGER RANGE 0 TO 5;
VARIABLE INDEX:INTEGER RANGE 0 TO 15;
VARIABLE DELAY:INTEGER RANGE 0 TO 10;
BEGIN
IF RST='0' THEN
NEXT_STATE:=0;
ELSIF CLK1'EVENT AND CLK1='1' THEN
IF Full_FIR='1' THEN
CASE NEXT_STATE IS
WHEN 0=>
TLC2543_CS<='0';
TLC2543_CLK<='0';
TLC2543_ADDRESS<="0000110000000000";
INDEX:=15;
NEXT_STATE:=1;
WHEN 1=>
NEXT_STATE:=2;
WHEN 2=>
TLC2543_CLK<='0';
TLC2543_OUT<=TLC2543_ADDRESS(INDEX);
IF INDEX >0 THEN
INDEX:=INDEX-1;
NEXT_STATE:=3;
ELSE
INDEX:=15;
NEXT_STATE:=4;
END IF;
WHEN 3=>
TLC2543_CLK<='1';
TLC2543_TMP_DATA(INDEX+1)<=TLC2543_IN;
NEXT_STATE:=2;
WHEN 4=>TLC2543_CLK<='1';
TLC2543_TMP_DATA(0)<=TLC2543_IN;
TLC2543_DATA_OUT<=TLC2543_TMP_DATA(15 DOWNTO 4);
DELAY:=10;
NEXT_STATE:=5;
WHEN 5=>
TLC2543_CLK<='0';
IF DELAY=0 THEN
TLC2543_CS<='1';
NEXT_STATE:=0;
ELSE
DELAY:=DELAY+1;
NEXT_STATE:=0;
END IF;
END CASE;
ELSE
NULL;
END IF;
END IF;
END PROCESS U2;
记录我的VHDL之路(三)
最新推荐文章于 2024-08-12 14:49:03 发布
本文详细记录了作者在使用VHDL进行数字逻辑设计时,如何构建并实现一个有限状态机的过程。通过实例解析,阐述了VHDL语法在描述状态机逻辑中的应用,涵盖了状态编码、状态转换图和状态机代码实现等关键步骤。
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