FPGA实现全加器

全加器

全加器是在半加器的基础上的升级版，除了加数和被加数加和外还要加上上一级传进来的进位信号。

原理图

代码实现

结合我之前的半加器博客，使用之前半加器的代码就可以实现全加器

module full_adder(
        input               in1,
        input               in2,
        input               cin,
        output              sum,
        output              count
    );
    
    wire        h0_sum;
    wire        h0_count;
    wire        h1_count;
    
harf_add harf_add_inst0(
                .in1    (in1),
                .in2    (in2),
                .sum    (h0_sum),
                .count  (h0_count)
        );
        
harf_add harf_add_inst1(
                .in1    (h0_sum),
                .in2    (cin),
                .sum    (sum),
                .count  (h1_count)
        );
        assign count = (h0_count | h1_count);
endmodule

RTL视图

仿真代码

module full_adder_tb();
    
    reg         in1;
    reg         in2;
    reg         cin;
    wire        sum;
    wire        count;
    
    parameter CLK_PERO = 20;
    initial begin
        in1 <= 0;
        in2 <= 0;
        cin <= 0;
    end
    
    full_adder full_adder_inst(
                   .in1     (in1  ),
                   .in2     (in2  ),
                   .cin     (cin  ),
                   .sum     (sum  ),
                   .count   (count)
    );
    always #(CLK_PERO / 2) in1 <= {$random} % 2; 
    always #(CLK_PERO / 2) in2 <= {$random} % 2; 
    always #(CLK_PERO / 2) cin <= {$random} % 2; 
    
    
    initial begin
        $timeformat(-9,0,"ns",6);
        $monitor("@time %t:in1=%b in2=%b cin=%b sum=%b count=%b",$time,in1,in2,cin,sum,count);
    end
endmodule

仿真波形