Chapter 19 Digital Phase-Locked Loops

Chapter 19 Digital Phase-Locked Loops

数字锁相环 Digital Phase-Locked Loops, 就是根据原来时钟信号, 产生新的时钟信号, which is locked or synchronized. (align 参考时钟边沿 or 在中间)

DPLL is termed a clock-recovery circuit or bit synchronization circuit

Phase Detector (PD) 分为 XOR PD和 PFD两种. XOR PD, 上升沿在data的中间. PFD上升沿在data开始

PLL主要模块: Phase Detector 类似EA, 放大 data in和dclock的 time difference. 送到 Loop filter. 经过Voltage-controlled oscillator (VCO). 这里有环路稳定性考量. DPLL不稳定的标准是the edge of output is not synchronized with the data, 即 not locked.

The Phase Detector

Phase Detector (PD) 分为 XOR PD和 PFD两种. XOR PD, 上升沿在data的中间. PFD上升沿在data开始.

The XOR Phase Detector

XOR PD 就是一个异或门 exclusive OR gate.

当Output of XOR PD 是50% duty cycle, 那就认为 DPLL in clock

经过RC filter(即Loop filter)后的电压送到VCO, 然后VCO输出CLOCK. Normal data input rate应该和VCO center frequency一致

3. DPLL lock 需要的时间取决于data pattern input和loop-filter

4. The XOR DPLL has good noise rejection.

5. The VCO operating frequency range should be limited to frequency much less than 2 $f_{clock}$ and much greater than 0.5$f_{clock}$, where $f_{clock}$ is the normal clock frequency for proper lock with a XOR PD.

6. A ripple on the output of the loop filter with a frequency equal to the clock frequency modulates the control voltage of the VCO.
   $$\Delta \varphi ={\varphi }_{data}-{\varphi }_{dclock}=\frac{\Delta t}{T_{dclock}}2\pi$$
   when in locked
   $$\Delta \varphi =\frac{\pi }{2}$$
   The average voltage out of phase detector is:
   $$V_{PDout}=K_{PD}\Delta \varphi$$
   The gain of PD is written as
   $$K_{PD}=\frac{VDD}{\pi }$$
   

   因此带XOR PD的VCO的设计标准:

   1. The center frequency, fcenter , should equal the clock frequency when the VCO control voltage is VDD/2.
   2. The maximum and minimum oscillation frequencies, fmax and fmin , of the VCO should be selected to avoid locking on harmonics of the input data.
   3. The VCO duty cycle is 50%. If this is not the case, the DPLL will have problems locking, or once locked the clock will jitter (move around in time).

The Phase Frequency Detector

当rising edge of data 先于 dclock rising edge, UP goes high, Down remain low. 导致dclock的频率增加, dclock追上data. 反之亦然.

Phase Frequency Detector (PFD)的特性:

1. A rising edge from the dclock and data must be present when making a phase comparison.
2. The widths of the dclock and the data are irrelevant.
3. The PFD will not lock on a harmonic of the data.
4. The outputs (Up and Down) of the PFD are both logic low when the loop is in lock, eliminating ripple on the output of the loop filter.
5. This PFD has poor noise rejection; a false edge on either the data or the dclock inputs drastically affects the output of the PFD.

PFD的output VPD需要能up 或者 down, 可用两种结构 Tri-State 和 Charge-Pump Output

Tri-state Loop filters:
$$TF=\frac{1+\frac{S}{Zero}}{1+\frac{S}{Pole}}$$

$$Zero=\frac{1}{R_{2}C}Pole=\frac{1}{(R_1+R_2)C}$$

For Slow variations in phase difference, Tri-state Loop filters 像integrator averaging the output of PD. For Fast variations , filters 像 resistor divider. 于是Tri-state Loop filter可以track fast variations in time difference between rising edges.

Charge-Pump Loop filters
$$TF=\frac{1+\frac{S}{Zero}}{1+\frac{S}{Pole}}$$

$$Zero=\frac{1}{R{C}_1}Pole=\frac{1}{\frac{(C_1{C}_2)}{C_1+C_2}R}$$

For Slow variations in phase difference, the current $I_{charge}$ linearly charges C1 and C2, 类似于averaging the effect. For Fast variations , charge pump就drive resistor (assuming C2 is small).

The Voltage-Controlled Oscillator

The design requirements of VCO used in PFD is more relaxed than XOR PD. $f_{center}=f_{clock}$不需要了, 但是在高速数据通信中还是用XOR PD更多

The gain of VCO:
$$K_{VCO}=2\pi \frac{f_{max}-f_{min}}{V_{max}-V_{min}}$$

The Current-Starved VCO

M2 和M3 是反相器, M1和M4提供电流.

上升t1下降t2时间, 对应VCO的频率

Linearizing the VCO’s gain

上图的问题在于VCO频率正比于ID, 而ID和Vgs即Vin_VCO成平方律关系, 为了让VCO频率线性正比于Vin_VCO, 可采用下图

M5R的W/L很大 (100/1), 因此Vgs5约等于Vth5, 和Vgs无关
$$I=\frac{V_{INvco}-V_{th}}{R}$$
这样电流就与输入电压成正比, 频率和输入电压成正比了

注意这个VCO的gain还是很高, 10mV voltage variation in VIN_vco gives a 2.5MHz variation in frequency.

For any low jitter PLL design, a VCO with low gain must be used.

Source Coupled VCOs

还有一种VCO 即 Source Coupled VCO. 相比current-starved VCO耗电更少, 但是需要电容.

a) NMOS 和 b) 作用类似, 只是b) 的ouput能到VDD, 而a) NMOS只能到VDD-Vth

工作原理:

假设M1 off, M2 on, M1 drain = Vdd-Vth = M2 gate, 因此M2 source = Vdd-2Vth, Output=Vdd-2Vth, 这是Output最小值. X一开始是Vdd-Vth, 但是The current through C, Id, cause X to discharge down to ground. 当X下降到Vdd-3Vth时, M1 由off -> on. 因此 X变化2Vth, 充电时间由C决定
$$\Delta t=C\frac{2Vthn}{I_D}$$

$$f_{osc}=\frac{1}{2\Delta t}=\frac{I_D}{4C\cdot Vthn}$$

波形图如下图所示

Loop Filter

Loop filter 确保VCO的输入电压 VinVCO 不发生抖动, 防止输出unlock.

我们关心两点: pull-in range 和lock range.

The pull-in range, $\pm \Delta {\omega }_P$ , is defined as the range of input frequencies that the DPLL will lock to. If the center frequency of the DPLL is 10 MHz and the pull-in range is 1 MHz, the DPLL will lock on an input frequency from 9 to 11 MHz in a time TP (assuming N = 1).

The lock range, $\pm \Delta {\omega }_L$ , is the range of frequencies in which the DPLL locks within one single beat note between the divided down output (dclock) and input (data) of the DPLL.
The operating frequency of the DPLL should be limited to the lock range for normal
operation.

XOR DPLL

Transfer Function:
$$H(s)=\frac{{\varphi }_{clock}}{{\varphi }_{data}}=\frac{K_{PD}{K}_F{K}_{VCO}}{s+\beta \cdot K_{PD}{K}_F{K}_{VCO}}$$

Active-PI Loop Filter

用二型补偿, Proportional Integral

PDF DPLL

Tri-State Output:

PFD using CMOS:

Charge Pump Output:

A CMOS implementation of a DPLL using charge pump is, in general, preferred over the tri-state output because of the better immunity to power supply variations.

Practical Implementation of the Charge Pump

Fig 19.36的问题是当M1或者M2 off, M1 source=GND, 等M1再想开启时, Current Sink需要建立时间才能达到Icharge (你不能指望从0V拉一个电流). 因此考虑Fig 19.37.

当Up=Down=L 时, M1L和M2L on, 电流从MPup经过M2L和M1L流向Mndwn. 当Up或Down=H, M2R或者M1R on, 从M12L切换到M12R. 唯一问题时Vx不一定等于Vy, 造成MPup或MNdwn前后电流不同. 为了解决切换时电流不变, 从Vy到Vx加一个buffer. 确保Vx=Vy.

Discussion

When selecting values for the loop filter, we assumed that the output resistance of the phase detector was small (for the XOR and tri-state PD) compared to the impedances used in the loop filter. We also assumed that the input resistance of the VCO was infinite and the input capacitance of the VCO was small compared to the capacitance used in the loop filter. Considering the parasitics present in the DPLL is an incredibly important part of the design. 注意各级输入输出阻抗和寄生电容.

The center frequency of the VCO is critical for good DPLL performance when using the XOR gate with RC loop filter. If the center frequency, fcenter , of the VCO (i.e., VinVCO = VDD/2) does not match twice the input data rate, the DPLL will lock up at a phase different from /2 (the input frequencies to any phase detector must be equal). The need for a precision center frequency is eliminated by using the XOR PD with an active- PI loop filter or by using the PFD. The other big benefit of using the PFD is that the VCO’s gain can be larger. 中心频率的讨论.

Finally, selecting of the loop’s damping factor, eta , is very important. If the value of eta is too small, the loop will have trouble locking or the output will jitter excessively when the loop is locked. This last problem is sometimes (gratuitously) called jitter peaking since a step in the DPLL’s input frequency causes excessive overshoot in VinVCO with small .

System Consideration

如果H增益下降可用equalizer把增益补偿上去.