HDL—Verilog Language—Vectors—Vector part select

A 32-bit vector can be viewed as containing 4 bytes (bits [31:24], [23:16], etc.). Build a circuit that will reverse the byte ordering of the 4-byte word.

AaaaaaaaBbbbbbbbCcccccccDddddddd => DdddddddCcccccccBbbbbbbbAaaaaaaa

This operation is often used when the endianness of a piece of data needs to be swapped, for example between little-endian x86 systems and the big-endian formats used in many Internet protocols.

一个32位矢量可以被视为包含4个字节（位[31:24]、[23:16]等）。构建一个电路，反转4字节字的字节顺序。

AaaaaaaBbbbbbbbcccccccccDddddddd => DdddddddCcccccccBbbbbbbbAaaaaaaa

当一段数据的端序需要交换时，例如在许多互联网协议中使用的小端x86系统和大端格式之间，经常使用此操作。

也是很简单，就是把输入的接口按他需要的顺序再给接出去就可以

module top_module(
    input [31:0] in,
    output [31:0] out );//
    // assign out[31:24] = ...;
        assign out[7:0] = in[31:24];
        assign out[15:8] = in[23:16];
        assign out[23:16] = in [15:8];
        assign out[31:24] = in[7:0];
endmodule