module uart_top(clk, nreset, rec, send, data);
input clk;
input nreset;
input rec;
output send;
parameter len = 16;
output [len:0]data;
uart_rec rec1( //底层模块1
.rec(rec),
.clk(clk),
.nreset(nreset),
.data(data)
);
uart_send send1(//底层模块2
.data(data),
.clk(clk),
.nreset(nreset),
.send(send)
);
endmodule
input clk;
input nreset;
input rec;
output send;
parameter len = 16;
output [len:0]data;
uart_rec rec1( //底层模块1
.rec(rec),
.clk(clk),
.nreset(nreset),
.data(data)
);
uart_send send1(//底层模块2
.data(data),
.clk(clk),
.nreset(nreset),
.send(send)
);
endmodule