VL14 自动贩售机1

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已于 2022-06-03 23:00:30 修改

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分类专栏： verilog 文章标签： fpga开发

于 2022-06-03 22:58:12 首次发布

本文链接：https://blog.csdn.net/ChenGz233/article/details/125117112

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VL14 自动贩售机1

先看状态转换图
在这里插入图片描述

这里，s0,s1,s2,s3,s4,s5,s6代表每一种状态，相邻之间差0.5元
out2则代表找钱

rtl代码：

`timescale 1ns/1ns
module seller1(
	input wire clk  ,
	input wire rst  ,
	input wire d1 ,
	input wire d2 ,
	input wire d3 ,
	
	output reg out1,
	output reg [1:0]out2
);
//*************code***********//
    parameter s0 = 3'd0;
    parameter s1 = 3'd1;
    parameter s2 = 3'd2;
    parameter s3 = 3'd3;
    parameter s4 = 3'd4;
    parameter s5 = 3'd5;
    parameter s6 = 3'd6;
    
    reg [2:0] cur;
    reg [2:0] nex;


    always @(posedge clk or negedge rst) begin
        if(rst == 1'b0) begin
            cur = s0;
            out1 = 0;
            out2 = 0;
        end
        else
            cur = nex;
    end
    
    always @(*) begin
        case(cur) 
            s0: begin
                if(d1) begin
                    nex = s1;
                    out1 = 0;
                    out2 = 0;
                end
                else if(d2)  begin
                    nex = s2;
                    out1 = 0;
                    out2 = 0;
                end
                else if(d3) begin
                    nex = s4;
                    out1 = 0;
                    out2 = 0;
                end
                else begin
                    nex = nex;
                    out1 = 0;
                    out2 = 0;
                end
            end
            s1: begin
                if(d1) begin
                    nex = s2;
                    out1 = 0;
                    out2 = 0;
                end
                else if(d2) begin
                    nex = s3;
                    out1 = 0;
                    out2 = 0;
                end
                else if(d3) begin
                    nex = s5;
                    out1 = 0;
                    out2 = 0;
                end
                else begin
                    nex = nex;
                    out1 = 0;
                    out2 = 0;
                end
            end
            s2:begin 
                if(d1) begin
                    nex = s3;
                    out1 = 0;
                    out2 = 0;
                end
                else if(d2) begin
                    nex = s4;
                    out1 = 0;
                    out2 = 0;
                end
                else if(d3) begin
                    nex = s6;
                    out1 = 0;
                    out2 = 0;
                end
                else begin
                    nex = nex;
                    out1 = 0;
                    out2 = 0;
                end
            end
            s3:begin 
                nex = s0;
                out1 = 1;
                out2 = 0;
            end
            s4:begin 
                nex = s0;
                out1 = 1;
                out2 = 1;
            end
            s5: begin 
                nex = s0;
                out1 = 1;
                out2 = 2;
            end
            s6: begin 
                nex = s0;
                out1 = 1;
                out2 = 3;
            end
            default: begin 
                nex = s0;

                end
        endcase
    end

//*************code***********//
endmodule

tesetbench代码

`timescale 1ns / 1ps


module seller1_tb();
    reg clk;
    reg rst;
    reg d1;
    reg d2;
    reg d3;
        
    wire out1;
    wire [1:0]out2;
    
 seller1 seller1_tb_1(
     .clk(clk),
     .rst(rst),
     .d1(d1),
     .d2(d2),
     .d3(d3),
     .out1(out1),
     .out2(out2)
 ); 
 real         CYCLE_200MHz = 5 ; //
    always begin
        clk = 0 ; #(CYCLE_200MHz/2) ;
        clk = 1 ; #(CYCLE_200MHz/2) ;
    end

initial begin
rst = 1'b0;
{d1,d2,d3}=3'b000;
#5;
rst = 1'b1;

@(posedge clk); {d1,d2,d3}=3'b100;
@(negedge clk); {d1,d2,d3}=3'b000;
#5
@(posedge clk); {d1,d2,d3}=3'b010;
@(negedge clk); {d1,d2,d3}=3'b000;
#5
@(posedge clk); {d1,d2,d3}=3'b100;
@(negedge clk); {d1,d2,d3}=3'b000;
#5
@(posedge clk); {d1,d2,d3}=3'b100;
@(negedge clk); {d1,d2,d3}=3'b000;
#5
@(posedge clk); {d1,d2,d3}=3'b001;
@(negedge clk); {d1,d2,d3}=3'b000;
#5
@(posedge clk); {d1,d2,d3}=3'b100;
@(negedge clk); {d1,d2,d3}=3'b000;
#5
@(posedge clk); {d1,d2,d3}=3'b010;
@(negedge clk); {d1,d2,d3}=3'b000;
#5
@(posedge clk); {d1,d2,d3}=3'b010;
@(negedge clk); {d1,d2,d3}=3'b000;
#5
@(posedge clk); {d1,d2,d3}=3'b001;
@(negedge clk); {d1,d2,d3}=3'b000;
#5
@(posedge clk); {d1,d2,d3}=3'b001;
@(negedge clk); {d1,d2,d3}=3'b000;
#5
$finish;
end

endmodule