课程学习——DC运行脚本

代码：

####################################################
#
#Name: prbs_dc.tcl
#Description: the synthesis tcl script for prbs code
#Date:2008-03-20
#Author: djy
#Version:v1.1
#Modified: 1-2008-01-24-modified the path since changing the workstation 
#          
###################################################

set src_path ./../00_source
set map_path ./mapped
set report_path ./report

###################
#begin time 
date

########################
#read source verilog code

read_verilog $src_path/control.v
read_verilog $src_path/counter_10.v
read_verilog $src_path/latch.v
read_verilog $src_path/freDetect.v

##################
#set & link top design ,remove relative constraints
current_design freDetect
link 
reset_design


################
#set clocks
create_clock -period 5 -name clk [get_ports clk_1Hz]
set_clock_latency -source 0.4 [get_clocks clk]
set_clock_latency 0.2 [get_clocks clk]
set_clock_uncertainty -setup 0.4 [get_clocks clk]
set_clock_transition 0.1 [get_clocks clk]
set_dont_touch_network [list clk ]

#set_dont_touch_network [all_clocks]


#########################
#advanced constraints
#foreach_in_collection clk1 [all_clocks] {
#   foreach_in_collection clk2 [remove_from_collection [all_clocks] [get_clocks $clk1]] {
#   set_false_path -from [get_clocks $clk1] -to [get_clocks $clk2] 
#   }
#}

################
#set input delays & output delays
set i_min_delay 0.4
set i_max_delay 1.2
set o_delay 0.4
set ain_ports [remove_from_collection [all_inputs]  [list clk_1Hz] ]
set_input_delay  -min $i_min_delay  -clock [get_clocks clk] $ain_ports
set_input_delay  -max $i_max_delay  -clock [get_clocks clk] $ain_ports
set_output_delay -max $o_delay -clock [get_clocks clk] [all_outputs]


################
#clk,reset,etc.driven capablity should be strongest
set_drive 0 [list tranpd_n]
set_drive 0 [get_ports clk_1Hz]
set_driving_cell -lib_cell BUFHD1X -library smic18_tt -pin Z [remove_from_collection $ain_ports [get_ports tranpd_n]]
set_load [expr [load_of smic18_tt/BUFHD1X/A]*8]  [all_outputs]
set_fanout_load 8 [all_outputs]

##############
#ensure the postive slack,the smallest area
set_max_area 0

#################
#report_lib 
set_operating_conditions typical            

#############
#wire_load_models 
set auto_wire_load_selection true
#set_wire_load_model -name CSM25_Conservative
set_wire_load_mode enclosed

##########
#area optimization
set compile_sequential_area_recovery true
set compile_new_boolean_structure true
set_structure -boolean true -boolean_effort high

###################
#flatten the whole design for area reducing
current_design prbs_top
ungroup -flatten -all
uniquify

############
#compile
compile
write -format verilog -hierarchy -output  $map_path/prbs_top_1st.sv
report_qor > $map_path/prbs_top_1st.qor
compile -map_effort high  -boundary_optimization -incr

################
#reports
check_design > $report_path/check_design.rpt
check_timing > $report_path/check_timing.rpt
report_timing -delay max -max_paths 10 -nets -tran -nosplit -input_pins > $report_path/timing_setup.rpt
report_timing -delay min -max_paths 10 -nets -tran -nosplit -input_pins > $report_path/timing_hold.rpt
report_clock > $report_path/clock.rpt
report_wire_load > $report_path/wlm.rpt
report_constraint -all_violators > $report_path/con_violators.rpt
report_area  > $report_path/area.rpt
report_net_fanout -nosplit -threshold 48 > $report_path/top_net_fanout.rpt


####################
#write the database
change_names -rule verilog -h
write -format verilog  -output $map_path/prbs_top.sv
write -format ddc -hierarchy -output $map_path/prbs_top.ddc
write_sdf        $map_path/prbs_top.sdf
write_sdc -v 1.4 $map_path/prbs_top.sdc

###################
#end time
date

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