DC脚本学习

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• man_flow.tcl

set SCRIPT_FILE  script #建立放置脚本文件
source ./$SCRIPT_FILE/set_env.tcl #设置环境变量

source -echo ./$SCRIPT_FILE/file_create.tcl #生成放置报告和结果的文件夹

set cache_write  WORK/$file_version
set cache_read   WORK/$file_version

# set COMPILE_OPTION "-no_autoungroup -scan"
if {$do_scan == 1} { #-scan 设置扫描链
    set COMPILE_OPTION [format "%s %s" -no_autoungroup -scan] 
    #no_autoungroup 关掉自动取消划分特性
} else {
    set COMPILE_OPTION [format "%s" -no_autoungroup]
}
set compile_cmd  "compile_ultra $CMP_OPTION"
alias do_compile $compile_cmd
alias do_compile_inc $compile_cmd -inc

set search_path [list \
            ./ \
            ../ \
            /opt/Synopsys/Synplify2015/libraries/syn/ \
            / opt/Synopsys/Synplify2015/dw/sim_ve/  \
            /opt/Foundary_Library/TSMC90/aci/sc-x/synopsys \
            /opt/Synopsys/Synplify2015/minpower/syn \
            /opt/Synopsys/Synplify2015/dw/syn_ver]

set synthetic_library {fast.db fast_leakage.db fastz.db slow.db typical.db typical_leakage.db}
set target_library {fast.db fast_leakage.db fastz.db slow.db typical.db typical_leakage.db}
set link_library {* fast.db fast_leakage.db fastz.db slow.db typical.db typical_leakage.db}
set symbol_library {generic.sdb}

#Files Direction


#set target_library   [list ${lib_slow}.db]
#set link_library     [list "*" ${lib_slow}.db]
#set synthetic_library [list standard.sldb]
#set symbol_library [list generic.sdb]

define_design_lib WORK -path ./WORK/$file_version

##################################################################
## Read in Verilog Files    ##
##################################################################

analyze -format sverilog  -vcs "-f $RTL_FILE/flist.f"
#read_verilog $RTL_FILE/Asynfifo.v
elaborate $working_design
#report_attributes -design
current_design $working_design
# link entity and block
link  

source -echo ./$SCRIPT_FILE/set_parameter.tcl

source -echo ./$SCRIPT_FILE/constraint_sdc.tcl
source -echo ./$SCRIPT_FILE/dont_touch.tcl
set_critical_range 0.2 [current_design]

#change naming rule

report_clock > $RPT_OUT/clock.syn.rpt
report_clock -skew >> $RPT_OUT/clock.syn.rpt

current_design $working_design

uniquify -force

##################################################################
## Optimization
##################################################################
change_names -rules verilog -hierarchy

#compile -map_effort high
#compile_ultra -no_autoungroup -inc

do_compile > $RPT_OUT/compile.rpt
do_compile_inc > $RPT_OUT/compile_inc.rpt
do_compile_inc > $RPT_OUT/compile_inc2.rpt
#
change_names -rules verilog -hierarchy
current_design $working_design

##########################################

check_design  > $RPT_OUT/check_design.rpt
check_timing  > $RPT_OUT/check_timing.rpt

report_qor > $RPT_OUT/qor.rpt

report_area > $RPT_OUT/area.rpt
report_area -hierarchy > $RPT_OUT/area_hier.rpt
report_timing   -loops > $RPT_OUT/timing_loop.rpt
report_timing -path full -net -cap -input -tran -delay min -max_paths 200 -nworst 200 > $RPT_OUT/timing.min.rpt
report_timing -path full -net -cap -input -tran -delay max -max_paths 200 -nworst 200 > $RPT_OUT/timing.max.rpt
report_constraints -all_violators -verbose > $RPT_OUT/constraints.rpt
report_power > $RPT_OUT/power.rpt
###################################################################
## Saving Hierarchy
###################################################################
set bus_naming_style {%s[%d]} 
write_file -f verilog -hierarchy -output $DATA_OUT/$working_design.v
write_sdf -version 2.1 $DATA_OUT/$working_design.sdf
write_file -f ddc -hierarchy -output $DATA_OUT/$working_design.ddc

write_sdc $DATA_OUT/$working_design.sdc

• set_env.tcl 设置环境变量

set RTL_FILE        source_file
set working_design  Asynfifo
set file_version    cp_test
set do_scan	    0

set RPT_DIR         RPT
set OUT_DIR         OUT

set RPT_OUT  [format "%s%s" $RPT_DIR/ $file_version]
set DATA_OUT [format "%s%s" $OUT_DIR/ $file_version]

set lib_slow      slow
set lib_fast      fast

• file_create.tcl 建立文件目录

 if {[file exist $RPT_DIR]} {
    echo "File $RPT_DIR already exist"
} else {
    exec mkdir $RPT_DIR
    echo "Creating $RPT_DIR !!!"
}

if {[file exist $RPT_DIR/$file_version]} {
    echo "File $file_version already exist"
    exec rm $RPT_DIR/$file_version -r
    exec mkdir $RPT_DIR/$file_version
    echo "Re-create $file_version files"
} else {
    exec mkdir $RPT_DIR/$file_version
    echo "Creating $file_version in $RPT_DIR !!!"
}


if {[file exist $OUT_DIR]} {
    echo "File $OUT_DIR already exist"
} else {
    exec mkdir $OUT_DIR
    echo "Creating $OUT_DIR !!!"
}

if {[file exist $OUT_DIR/$file_version]} {
    echo "File $file_version already exist"
    exec rm $OUT_DIR/$file_version -r
    exec mkdir $OUT_DIR/$file_version
    echo "Re-create $file_version files"
} else {
    exec mkdir $OUT_DIR/$file_version
    echo "Creating $file_version in $OUT_DIR !!!"
}

# create work
if {[file exist WORK]} {
    echo "File WORK already exist"
} else {
    exec mkdir WORK
    echo "Creating WORK!!!"
}

if {[file exist WORK/$file_version]} {
    echo "File WORK/$file_version already exist"
} else {
    exec mkdir WORK/$file_version
    echo "Creating WORK/$file_version in WORK !!!"
}

• constranit_sdc.tcl 延时时钟约束

-set compile_enable_constant_propagation_with_no_boundary_opt false
set timing_enable_multiple_clocks_per_reg true
set enable_recovery_removal_arcs true

create_clock -name CLK_R  -p 12 [get_ports rd_clk] -waveform {0 5}
create_clock -name CLK_W  -p 20 [get_ports wr_clk] -waveform {2 10}

set_clock_uncertainty 0.5 CLK_R
set_clock_uncertainty 0.6 CLK_W

set_clock_groups -asynchronous -group CLK_R
set_clock_groups -asynchronous -group CLK_W

set_max_transition  1.4 [current_design]
set_max_transition  -clock_path 0.90 [all_clocks]
set_clock_transition 0.9 [all_clocks]
set_input_transition 0.89 [all_inputs]

set_driving_cell -lib_cell BUFHDV24 [all_inputs]
set_load [load_of ${lib_slow}/BUFHDV24/I] [all_outputs]

#set_input_delay 3 -clock CLK_W DATA_WRT
#set_input_delay -max 7 -clock CLK_R  {RD_EN}
#set_input_delay -min 2 -clock CLK_R  {RD_EN}
#set_output_delay 1 -clock CLK_R DATA_RD*


#set_multicycle_path -setup  2 -from A -to B
#set_multicycle_path -hold   1 -from A -to B

# false path
set_false_path -from [get_ports rst]

• set_parameter.tcl

##################################################################
## Compile variable##
##################################################################
set write_name_nets_same_as_ports true
set compile_assume_fully_decoded_three_state_buses true
set verilogout_no_tri true
set compile_no_new_cells_at_top_level false
set compile_preserve_sync_resets true
## Remove assign statements when generating gate level netlist 
set compile_fix_multiple_port_nets true

# for async reset timing check
set enable_recovery_removal_arcs true
set_fix_multiple_port_nets -all -buffer_constants
#set_fix_multiple_port_nets -all

#/******************************************************************
#****                         HDL RULES                          ***
#*******************************************************************/
set hdlin_check_no_latch                        true
set hdlin_suppress_warnings                     false
set hdlin_ff_always_sync_set_reset              true
set hdlin_infer_mux                             default
set hdlin_keep_signal_name                      all_driving
set hdlin_on_sequential_mapping                 false
set compile_delete_unloaded_sequential_cells    true
set hdlin_preserve_sequential                   none

#/******************************************************************
#****         VERILOG RULES: VERILOG OUT                        **** 
#*******************************************************************/
set verilogout_show_unconnected_pins            true
set verilogout_no_tri                           true
set verilogout_single_bit                       false
set verilogout_equation                         false

#/******

#/******************************************************************
#****                    Scan Options                           ***
#*******************************************************************/
set insert_test_design_naming_style             "%s_%d"
#set test_scan_in_port_naming_style              "SI%s%s"
#set test_scan_enable_port_naming_style          "SCN%s"
#set test_scan_out_port_naming_style             "SO%s%s"

• set_dont_touch.tcl

# set_dont_touch [get_cells ram_dual/**]