全减器的门电路与真值表
![门电路形式](https://i-blog.csdnimg.cn/blog_migrate/2c3690591fcab74564d910838c1c61ba.png)
![真值表](https://i-blog.csdnimg.cn/blog_migrate/25d27e66129468304a9ad4c8b6b8e2b9.png)
四种描述代码
module way1(a,b,in,di,out);//门电路层次
input a,b,in;
output di,out;
not(n1,a);
and(a1,b,n1);
xor(x1,a,b);
xor(di,in,x1);
not(n2,x1);
and(a2,in,n2);
or(out,a2,a1);
endmodule
module way2(a,b,in,di,out);//行为层次
input a,b,in;
output reg di,out;
always @(*)
begin
case ({a,b,in})
3'b000 :begin di= 0;out = 0; end
3'b001 :begin di= 1;out = 1; end
3'b010 :begin di= 1;out = 1; end
3'b011 :begin di= 1;out = 0; end
3'b100 :begin di= 0;out = 1; end
3'b101 :begin di= 0;out = 0; end
3'b110 :begin di= 0;out = 0; end
3'b111 :begin di= 1;out = 1; end
endcase
end
endmodule
module way3(a,b,in,di,out);//数据流层次
input a,b,in;
output out,di;
assign out = (~a&b)|(~(a^b)&in);
assign di = in^(a^b);
endmodule
激励文件
`timescale 1ns/1ns
module test();
reg a,b,in;
wire out,di;
way4 i1(
.a(a),
.b(b),
.in(in),
.di(di),
.out(out)
);
initial
begin
a=1'b0;
b=1'b0;
in=1'b0;
# 100;
a=1'b0;
b=1'b0;
in=1'b1;
# 100;
a=1'b0;
b=1'b1;
in=1'b1;
# 100;
a=1'b1;
b=1'b1;
in=1'b1;
# 100;
$stop;
end
endmodule