/* Memory mapping of Cortex-M4 Hardware */#defineSCS_BASE(0xE000E000UL)/*!< System Control Space Base Address */#defineSysTick_BASE(SCS_BASE +0x0010UL)/*!< SysTick Base Address */#defineNVIC_BASE(SCS_BASE +0x0100UL)/*!< NVIC Base Address */#defineSCB_BASE(SCS_BASE +0x0D00UL)/*!< System Control Block Base Address */#defineSCnSCB((SCnSCB_Type *) SCS_BASE )/*!< System control Register not in SCB */#defineSCB((SCB_Type *) SCB_BASE )/*!< SCB configuration struct */#defineSysTick((SysTick_Type *) SysTick_BASE )/*!< SysTick configuration struct */#defineNVIC((NVIC_Type *) NVIC_BASE )/*!< NVIC configuration struct */