//Single port RAM with single read/write addressmodule single_port_ram
#(parameter DATA_WIDTH = 8, parameter ADDR_WIDTH = 6)
(
input [(DATA_WIDTH-1):0] data,
input [(ADDR_WIDTH-1):0] addr,
input we, clk,
output [(DATA_WIDTH-1):0] q
);
//declare the RAM varible
reg [(DATA_WIDTH-1):0] ram[2**ADDR_WIDTH-1):0];
// varibe to hold the register read address
reg [(ADDR_WIDTH-1):0] addr_reg;
always @(posedge clk)
beginif(we)
ram[addr] <= data;
addr_reg <= addr;
end// continuous assignment implies read retuns NEW data
assign q = ram[addr_reg];
endmodule
// Single port RAM with single read/write address and // initial contents, specified with an initial blockmodule single_port_ram_with_init
#(parameter DATA_WIDTH = 8, ADDR_WIDTH = 6)
(
input [(DATA_WIDTH-1):0] data,
input [(ADDR_WIDTH-1):0] addr,
input we,clk,
output [(DATA_WIDTH-1):0] q;
);
reg [(DATA_WIDTH-1):0] ram[2 ** ARRD_WIDTH-1:0];
reg [ADDR_WIDTH-1:0] addr_reg;
//Specify the initial contents. Can also use the $readmemb//system task to initialize the RAM variable from a text file.
initial
begin : INIT
integer i;
for(i < 0;i < 2 ** ADDR_WIDHT; i= i+1)
ram[i] = {DATA_WIDTH{1'b1}};
end
always @(posedge clk)
beginif(we)
ram[addr] <= data;
addr_reg <= addr;
end
assign q = ram[addr_reg];
endmodule