存储器RAM与ROM（Verilog HDL 虚拟实验）

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最新推荐文章于 2023-08-18 10:55:08 发布

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分类专栏： System Verilog 文章标签： fpga 寄存器 systemverilog

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索引

一、RAM设计
- 顶层设计：
- RAM模块：
利用ROM存取七段数码管的真值
- ROM实现
- 顶层模块：

一、RAM设计

顶层设计：

RAM演示

`default_nettype none 
module VirtualBoard (
    input  logic  CLOCK,      // 10 MHz Input Clock 
    input  logic [19:0] PB,   // 20 Push Buttons, logical 1 when pressed
    input  logic [35:0] S,    // 36 Switches
    output logic [35:0] L,    // 36 LEDs, drive logical 1 to light up
    output logic  [7:0] SD7,  // 8 common anode Seven-segment Display
    output logic  [7:0] SD6,
    output logic  [7:0] SD5,
    output logic  [7:0] SD4,
    output logic  [7:0] SD3,
    output logic  [7:0] SD2,
    output logic  [7:0] SD1,
    output logic  [7:0] SD0
);
/********* Seven-segment decoder instantiation **********/
logic [3:0] HD[7:0];  // 8 hexadecimal display 
SevenSegDecode ssdecode_inst7(.iData(HD[7]), .oSeg(SD7));
SevenSegDecode ssdecode_inst6(.iData(HD[6]), .oSeg(SD6));
SevenSegDecode ssdecode_inst5(.iData(HD[5]), .oSeg(SD5));
SevenSegDecode ssdecode_inst4(.iData(HD[4]), .oSeg(SD4));
SevenSegDecode ssdecode_inst3(.iData(HD[3]), .oSeg(SD3));
SevenSegDecode ssdecode_inst2(.iData(HD[2]), .oSeg(SD2));
SevenSegDecode ssdecode_inst1(.iData(HD[1]), .oSeg(SD1));
SevenSegDecode ssdecode_inst0(.iData(HD[0]), .oSeg(SD0));

/** The input port is replaced with an internal signal **/
wire reset  = PB[0];
wire clk    = PB[1];
wire [3:0] write_data  = S[11:8];
wire [1:0] WAress = S[5:4];
wire write_enable = S[6];
wire [1:0] RAddress1= S[1:0];
wire [1:0] RAddress2= S[3:2];
logic [3:0] read_data1,read_data2;

/************* The logic of this experiment *************/
RAM #(.ADDRWIDTH(2), .DATAWIDTH(4)) mem(.iClk(clk), .iWR(write_enable), .iWA(WAress),
    .iRA1(RAddress1), .iRA2(RAddress2),.iWriteData(write_data), .oReadData1(read_data1),.oReadData2(read_data2));

/****** Internal signal assignment to output port *******/

assign HD[4] = read_data1[3:0];
assign HD[5] = read_data2[3:0];

endmodule

RAM模块：

module RAM
#(  parameter ADDRWIDTH = 5,
	  parameter DATAWIDTH = 32)
(
	input  wire iClk, iWR,
	input  wire [ADDRWIDTH-1:0] iWA,iRA1,iRA2,
  input  wire [DATAWIDTH-1:0] iWriteData,
  output wire [DATAWIDTH-1:0] oReadData1,oReadData2
);
  localparam MEMDEPTH = 1<<ADDRWIDTH; //存储器的字数 
  logic [DATAWIDTH-1:0] mem[0:MEMDEPTH-1];

  always_ff @(posedge iClk)
  begin
    if (iWR)
	  begin
	   if(iWA != 00)
      mem[iWA] <= iWriteData;
		else
		 mem[iWA] <= 0;
	  end
  end

  assign oReadData1 = mem[iRA1]; // 读地址未锁存，编译器使用FPGA的逻辑资源生成存储器
  assign oReadData2 = mem[iRA2];
	 
endmodule

利用ROM存取七段数码管的真值

ROM实现七段数码管

ROM实现

示例：

module ROM
#(  parameter ADDRWIDTH = 4,
	parameter DATAWIDTH = 8)
(
    input  logic [ADDRWIDTH-1:0] iAddress,
    output logic [DATAWIDTH-1:0] oData
);
    localparam MEMDEPTH = 1<<ADDRWIDTH;
    logic [DATAWIDTH-1:0] mem[0:MEMDEPTH-1];
    assign oData = mem[iAddress];

    initial begin
        /*$readmemb("init_mem.txt",mem); // 如果文件中的数据是十六进制，用 $readmemh 
        也可以采用如下代码代替上面的readmemh*/
		  mem[4'h00] = 8'b11000000;
        mem[4'h01] = 8'b11111001;
		  mem[4'h02] = 8'b10100100;
		  mem[4'h03] = 8'b10110000;
		  mem[4'h04] = 8'b10011001;
		  mem[4'h05] = 8'b10010010;
        mem[4'h06] = 8'b10000010;
		  mem[4'h07] = 8'b11111000;
		  mem[4'h08] = 8'b10000000;
		  mem[4'h09] = 8'b10010000;
		  mem[4'h0A] = 8'b10001000;
		  mem[4'h0B] = 8'b10000011;
		  mem[4'h0C] = 8'b11000110;
		  mem[4'h0D] = 8'b10100001;
		  mem[4'h0E] = 8'b10000110;
		  mem[4'h0F] = 8'b10001110;
    end

endmodule

顶层模块：

`default_nettype none 
module VirtualBoard (
    input  logic  CLOCK,      // 10 MHz Input Clock 
    input  logic [19:0] PB,   // 20 Push Buttons, logical 1 when pressed
    input  logic [35:0] S,    // 36 Switches
    output logic [35:0] L,    // 36 LEDs, drive logical 1 to light up
    output logic  [7:0] SD7,  // 8 common anode Seven-segment Display
    output logic  [7:0] SD6,
    output logic  [7:0] SD5,
    output logic  [7:0] SD4,
    output logic  [7:0] SD3,
    output logic  [7:0] SD2,
    output logic  [7:0] SD1,
    output logic  [7:0] SD0
); 

  wire [3:0] HEXData = S[11:8];
  wire [7:0] SegData ;
  ROM ssdecode_inst(.iAddress(HEXData),.oData(SegData));
  assign L[7:0] = SegData;
  assign SD1 = SegData;
  


endmodule