伪双口RAM

module dual_ram#(
    parameter    DATA_WIDTH = 8,
    parameter    ADDR_WIDTH = 8,
    parameter    MEM_DEPTH = 256    
)
(
    clk, rst_n, cs_n, write_en_a, write_en_b, 
    read_en_a, read_en_b, addr_a, addr_b,
    din_a, din_b, dout_a, dout_b 
);

input    clk;
input    rst_n;
input    cs_n;
input    write_en_a;
input    write_en_b;
input[ADDR_WIDTH-1：0]    addr_a, addr_b;
input[DATA_WIDTH-1:0]     din_a, din_b;
output[DATA_WIDTH-1:0]    dout_a, dout_b;

reg[DATA_WIDTH-1:0]    dout_a, dout_b;
reg[DATA_WIDTH-1:0]    mem[0:MEM_DEPTH-1];
integer    i;

always@(posedge clk or negedge rst_n)begin
    if(!rst_n)
        for(i=0; i<MEM_DEPTH-1; i=i+1)
            mem[i] <= 'b0;
    else if(!cs_n && write_en_a && !write_en_b)
            mem[addr_a] <= din_a;
         else if(!cs_n && !write_en_a && write_en_b)
                mem[addr_b] <= din_b;
end

always@(posedge clk or negedge rst_n)begin
    if(!rst_n)begin
        dout_a <= 'b0;
        dout_b <= 'b0;
    end
    else if(!cs_n && read_en_a && !read_en_b)
            dout_a <= mem[addr_a];
         else if(!cs_n && !read_en_a && read_en_b)
                dout_b <= mem[addr_b];
end

endmodule