Cyclic redundancy check calculation unit (CRC)

1 Introduction
The CRC (cyclic redundancy check) calculation unit is used to get a CRC code from 8-, 16- or 32-bit data word and a generator polynomial.
Among other applications, CRC-based techniques are used to verify data transmission or storage integrity. In the scope of the functional safety standards, they offer a means of verifying the Flash memory integrity. The CRC calculation unit helps compute a signature
of the software during runtime, to be compared with a reference signature generated at link time and stored at a given memory location.
2 CRC main features
• Fully programmable polynomial with programmable size (7, 8, 16, 32 bits)
• Handles 8-,16-, 32-bit data size
• Programmable CRC initial value
• Single input/output 32-bit data register
• Input buffer to avoid bus stall during calculation
• CRC computation done in 4 AHB clock cycles (HCLK) for the 32-bit data size
• General-purpose 8-bit register (can be used for temporary storage) • Reversibility option on I/O data

3 CRC functional description
3.1 CRC block diagram
Figure 7. CRC calculation unit block diagram

3.2 CRC internal signals
Table 15. CRC internal input/output signals
3.3 CRC operation
The CRC calculation unit has a single 32-bit read/write data register (CRC_DR). It is used to input new data (write access), and holds the result of the previous CRC calculation (read access).
Each write operation to the data register creates a combination of the previous CRC value (stored in CRC_DR) and the new one. CRC computation is done on the whole 32-bit data word or byte by byte depending on the format of the data being written.
The CRC_DR register can be accessed by word, right-aligned half-word and right-aligned byte. For the other registers only 32-bit access is allowed.
The duration of the computation depends on data width:
• 4 AHB clock cycles for 32-bit
• 2 AHB clock cycles for 16-bit
• 1 AHB clock cycles for 8-bit

An input buffer allows to immediately write a second data without waiting for any wait states due to the previous CRC calculation.
The data size can be dynamically adjusted to minimize the number of write accesses for a given number of bytes. For instance, a CRC for 5 bytes can be computed with a word write followed by a byte write.
The input data can be reversed, to manage the various endianness schemes. The reversing operation can be performed on 8 bits, 16 bits and 32 bits depending on the REV_IN[1:0] bits
in the CRC_CR register.
For example: input data 0x1A2B3C4D is used for CRC calculation as:
0x58D43CB2 with bit-reversal done by byte
0xD458B23C with bit-reversal done by half-word
0xB23CD458 with bit-reversal done on the full word
The output data can also be reversed by setting the REV_OUT bit in the CRC_CR register.
The operation is done at bit level: for example, output data 0x11223344 is converted into
0x22CC4488.
The CRC calculator can be initialized to a programmable value using the RESET control bit in the CRC_CR register (the default value is 0xFFFFFFFF).
The initial CRC value can be programmed with the CRC_INIT register. The CRC_DR register is automatically initialized upon CRC_INIT register write access.
The CRC_IDR register can be used to hold a temporary value related to CRC calculation.
It is not affected by the RESET bit in the CRC_CR register.
Polynomial programmability
The polynomial coefficients are fully programmable through the CRC_POL register, and the polynomial size can be configured to be 7, 8, 16 or 32 bits by programming the POLYSIZE[1:0] bits in the CRC_CR register. Even polynomials are not supported.
If the CRC data is less than 32-bit, its value can be read from the least significant bits of the CRC_DR register.
To obtain a reliable CRC calculation, the change on-fly of the polynomial value or size can not be performed during a CRC calculation. As a result, if a CRC calculation is ongoing, the application must either reset it or perform a CRC_DR read before changing the polynomial.
The default polynomial value is the CRC-32 (Ethernet) polynomial: 0x4C11DB7.