FPGA 任意分频器设计

结合网上的经验，自己写了写偶、奇、任意分频器的程序。
偶分频器

/************************* Date:2018.8.14**************************************
****************************Vision:V1.0**************************************/

module Divide_even(CLK,RST,CLK_EVEN);

input CLK;
input RST;
output CLK_EVEN;

reg CLK_EVEN;
reg [5:0] CNT;//分频计数器,该寄存器的大小由待分频的数决定。
parameter N=6;//待分频数

always @(posedge CLK or negedge RST)
    begin
        if (!RST)
            begin
            CNT<=0;
            CLK_EVEN<=0;
            end
        else
            begin
                if (CNT==N/2-1)
                    begin
                    CLK_EVEN<=~CLK_EVEN;
                    CNT<=0;
                    end
                else
                    begin
                    CNT<=CNT+1;
                    end
            end
    end
endmodule

testbench文件

`timescale 1 ns/ 1 ns
module Divide_even_vlg_tst();

reg RST;
reg CLK;

wire CLK_EVEN;

Divide_even i1 (
   .RST(RST),
    .CLK(CLK),
    .CLK_EVEN(CLK_EVEN)
);
    initial                                                
        begin                                                                         
            CLK=0;
            forever  #50 CLK=~CLK;                     
        end                                                    

    initial
        begin
            RST=0;
            #1000 RST=1;
        end

endmodule

奇分频器
/*************** Date:2018.8.14**************************************
***********************Vision:V1.0*********************************/

module Divide_odd(CLK,RST,CLK_OUT);

input RST;
input CLK;
output CLK_OUT;

parameter N=5;

reg CLK_POS;
reg [5:0]CNT_POS;

always @(posedge CLK or negedge RST)
    begin
        if (!RST)
            begin
                CLK_POS<=0;
                CNT_POS<=0;
            end
        else
            begin
                if(CNT_POS==(N-1)/2)
                    begin
                        CLK_POS<=~CLK_POS;
                        CNT_POS<=CNT_POS+1;
                    end
                else if(CNT_POS==(N-1))
                    begin
                       CLK_POS<=~CLK_POS;
                        CNT_POS<=0;
                    end
                else
                    begin
                        CLK_POS<=CLK_POS;
                        CNT_POS<=CNT_POS+1;
                    end
            end
        end

reg CLK_NEG;
reg [5:0]CNT_NEG;       

always @(negedge CLK or negedge RST)
    begin
    if (~RST)
        begin
            CLK_NEG<=0;
            CNT_NEG<=0;
        end
    else
        begin
            if(CNT_NEG==(N-1)/2)
                begin
                    CNT_NEG<=CNT_NEG+1;
                    CLK_NEG<=~CLK_NEG;
                end
            else if(CNT_NEG==(N-1))
                begin
                    CNT_NEG<=0;
                    CLK_NEG<=~CLK_NEG;
                end
            else
                begin
                    CNT_NEG<=CNT_NEG+1;
                    CLK_NEG<=CLK_NEG;
                end
        end
    end

assign CLK_OUT=CLK_NEG | CLK_POS;

endmodule

testbench文件

`timescale 1 ns/ 1 ns
module Divide_odd_vlg_tst();

reg CLK;
reg RST;

wire CLK_OUT;

Divide_odd i1 (

    .CLK(CLK),
    .CLK_OUT(CLK_OUT),
    .RST(RST)
);
initial                                                
    begin
      CLK=0;
      forever #50
      CLK=~CLK;                             
    end                                                    

initial
    begin
    RST=0;
    #1000 RST=1;
    end                                                
endmodule

任意分频器

/************************* Date:2018.8.14**************************************
****************************Vision:V1.0**************************************/
module Divide_any(RST,CLK,CLK_OUT);

input RST,CLK;
output CLK_OUT;

parameter K=4;

reg CLK_POS;
reg [3:0] CNT_POS;
always @(posedge CLK or negedge RST)
    begin
        if(!RST)
            begin
                CLK_POS<=0;
                CNT_POS<=0;
            end
        else
            begin
                if (CNT_POS==K-1)
                    begin
                        CLK_POS<=~CLK_POS;
                        CNT_POS<=0;
                    end
                **else if(CNT_POS==(K>>1)-1)**
                    begin
                        CLK_POS<=~CLK_POS;
                        CNT_POS<=CNT_POS+1;
                    end
                else
                    begin
                        CNT_POS<=CNT_POS+1;
                        CLK_POS<=CLK_POS;
                    end 
            end
    end

reg CLK_NEG;
reg [3:0] CNT_NEG;
always @(negedge CLK or negedge RST)    
    begin
        if (!RST)
            begin
                CLK_NEG<=0;
                CNT_NEG<=0;
            end
        else
            begin
                if(CNT_NEG==K-1)
                    begin
                        CLK_NEG<=~CLK_NEG;
                        CNT_NEG<=0;
                    end
                else if (CNT_NEG==(K>>1)-1)
                    begin
                        CLK_NEG<=~CLK_NEG;
                        CNT_NEG<=CNT_NEG+1;
                    end
                else
                    begin
                        CLK_NEG<=CLK_NEG;
                        CNT_NEG<=CNT_NEG+1;
                    end
            end
    end

assign CLK_OUT=(K%2)?(CLK_POS&CLK_NEG):(CLK_POS);   
endmodule 

testbench文件

`timescale 1 ns/ 1 ns
module Divide_any_vlg_tst();

reg CLK;
reg RST;

wire CLK_OUT;


Divide_any i1 ( 
    .CLK(CLK),
    .CLK_OUT(CLK_OUT),
    .RST(RST)
);
initial                                                
    begin                                                                         
        CLK=0;
        forever  #50 CLK=~CLK;                     
    end 

initial                
    begin                                                  
        RST=0;
        #1000 RST=1;
    end                                                    
endmodule