目录
016_Vector Concatenation Operator
021_Connection Port By Postion
029_Always Blocks(Combinational)
035_Priority Encoder With Casez
037_Conditional Ternary Operator
039_Reduction: Even Wider Gates
040_Combinational For-Loop: Vector Reversal 2
041_Combination For-Loop: 255-bit Population Count
042_Generate For-Loop: 100-bit binary adder 2
043_Generate For-Loop: 100-digit BCD adder
-1_Preview
0_Getting Started
001_Step One
module top_module( output one ); // Insert your code here assign one = 1'b1; endmodule
002_Output Zero
module top_module( output zero );// Module body starts after semicolon assign zero = 1'b0; endmodule
1_Basic
003_Simple Wire
module top_module( input in, output out ); assign out = in; endmodule
004_Four Wires
module top_module( input a,b,c, output w,x,y,z ); assign w = a; assign x = b; assign y = b; assign z = c; endmodule
005_Inverter
module top_module( input in, output out ); assign out = ~in; endmodule
006_AND Gate
module top_module( input a, input b, output out ); assign out = a & b; endmodule
007_Nor Gate
module top_module( input a, input b, output out ); assign out = ~(a|b); endmodule
008_XNOR Gate
module top_module( input a, input b, output out ); assign out = ~(a^b); //assign out = (a&b) | (~a&~b); endmodule
009_Declaring Wires
`default_nettype none module top_module( input a, input b, input c, input d, output out, output out_n ); wire A1,A2,A3; assign A1 = a & b; assign A2 = c & d; assign A3 = A1 | A2; assign out = A3; assign out_n = ~A3; endmodule
010_7458 Chip
module top_module ( input p1a, p1b, p1c, p1d, p1e, p1f, output p1y, input p2a, p2b, p2c, p2d, output p2y ); assign p2y = (p2a&p2b)|(p2c&p2d); assign p1y = (p1a&p1b&p1c)|(p1d&p1e&p1f); endmodule
2_Vectors
011_Vectors
module top_module ( input wire [2:0] vec, output wire [2:0] outv, output wire o2, output wire o1, output wire o0 ); // Module body starts after module declaration assign outv = vec; assign o2 = vec[2]; assign o1 = vec[1]; assign o0 = vec[0]; endmodule
012_Vectors IN More Detail
`default_nettype none // Disable implicit nets. Reduces some types of bugs. module top_module( input wire [15:0] in, output wire [7:0] out_hi, output wire [7:0] out_lo ); assign out_hi = in[15:8]; assign out_lo = in[ 7:0]; endmodule
013_Vector Part Select
module top_module( input [31:0] in, output [31:0] out );// // assign out[31:24] = ...; assign out[31:24] = in[ 7: 0]; assign out[23:16] = in[15: 8]; assign out[15: 8] = in[23:16]; assign out[ 7: 0] = in[31:24]; //assign out = {in[7:0], in[15:8], in[23:16], in[31:24]}; endmodule
014_Bitwise Operators
module top_module( input [2:0] a, input [2:0] b, output [2:0] out_or_bitwise, output out_or_logical, output [5:0] out_not ); assign out_or_bitwise = a | b; assign out_or_logical = a || b; assign out_not[5:0] = {~b,~a}; endmodule
015_Four-Input Gates
module top_module( input [3:0] in, output out_and, output out_or, output out_xor ); assign out_and = in[3] & in[2] & in[1] & in[0]; assign out_or = in[3] | in[2] | in[1] | in[0]; assign out_xor = in[3] ^ in[2] ^ in[1] ^ in[0]; endmodule
016_Vector Concatenation Operator
module top_module ( input [4:0] a, b, c, d, e, f, output [7:0] w, x, y, z );// // assign { ... } = { ... }; assign w = {a[4:0],b[4:2]}; assign x = {b[1:0],c[4:0],d[4:4]}; assign y = {d[3:0],e[4:1]}; assign z = {e[0:0],f[4:0],2'b11}; //assign {w, x, y, z} = {a, b, c, d, e, f, 2'b11}; endmodule
017_Vector Reversal 1
module top_module( input [7:0] in, output [7:0] out ); assign out = {in[0],in[1],in[2],in[3],in[4],in[5],in[6],in[7]}; endmodule
018_Replication Operator
module top_module ( input [7:0] in, output [31:0] out );// // assign out = { replicate-sign-bit , the-input }; assign out = {{24{in[7]}},in}; endmodule
⚠️ NO Figure Reply.
# Hint: Output 'out' has no mismatches. # Hint: Total mismatched samples is 0 out of 98 samples
019_More Replication
module top_module ( input a, b, c, d, e, output [24:0] out );// // The output is XNOR of two vectors created by // concatenating and replicating the five inputs. // assign out = ~{ ... } ^ { ... }; assign out = {~{5{a}}^{a,b,c,d,e},~{5{b}}^{a,b,c,d,e},~{5{c}}^{a,b,c,d,e},~{5{d}}^{a,b,c,d,e},~{5{e}}^{a,b,c,d,e}}; endmodule
⚠️ NO Figure Reply.
# Hint: Output 'out' has no mismatches. # Hint: Total mismatched samples is 0 out of 98 samples
3_Modules:Hierarchy
020_Modules
module top_module ( input a, input b, output out ); mod_a instance1(.out(out),.in1(a),.in2(b)); endmodule
021_Connection Port By Postion
module top_module ( input a, input b, input c, input d, output out1, output out2 ); mod_a instance1(out1,out2,a,b,c,d); endmodule
022_Connect Nets By Name
module top_module ( input a, input b, input c, input d, output out1, output out2 ); mod_a instance1(.in1(a),.in2(b),.in3(c),.in4(d),.out1(out1),.out2(out2)); endmodule
023_Three Modules
module top_module ( input clk, input d, output q ); wire q1,q2; my_dff instance1(.clk(clk),.d( d),.q(q1)); my_dff instance2(.clk(clk),.d(q1),.q(q2)); my_dff instance3(.clk(clk),.d(q2),.q( q)); endmodule
024_Modules and Vectors
module top_module ( input clk, input [7:0] d, input [1:0] sel, output [7:0] q ); wire [7:0] q1,q2,q3; my_dff8 instance1(.clk(clk),.d( d),.q(q1)); my_dff8 instance2(.clk(clk),.d(q1),.q(q2)); my_dff8 instance3(.clk(clk),.d(q2),.q(q3)); always @(*)begin case(sel) 0 : q=d; 1 : q=q1; 2 : q=q2; 3 : q=q3; endcase end endmodule
025_Adder1
module top_module( input [31:0] a, input [31:0] b, output [31:0] sum ); wire carry1,carry2; wire [15:0] sum1; wire [15:0] sum2; add16 instance1(.a(a[15:0]),.b(b[15:0]),.cin(0),.cout(carry1),.sum(sum1)); add16 instance2(.a(a[31:16]),.b(b[31:16]),.cin(carry1),.cout(carry2),.sum(sum2)); assign sum = {sum2,sum1}; endmodule
026_Adder2
//Ref module top_module ( input [31:0] a, input [31:0] b, output [31:0] sum );// wire carry1,carry2; wire [15:0] sum1; wire [15:0] sum2; add16 instance1(.a(a[15:0]),.b(b[15:0]),.cin(0),.cout(carry1),.sum(sum1)); add16 instance2(.a(a[31:16]),.b(b[31:16]),.cin(carry1),.cout(carry2),.sum(sum2)); assign sum = {sum2,sum1}; endmodule module add1 ( input a, input b, input cin, output sum, output cout ); // Full adder module here always @(*) begin if(!cin) begin if(a==0 && b==0)begin sum = 0; cout = 0; end else if((a==0 && b==1) || (a==1 && b==0))begin sum = 1; cout = 0; end else begin sum = 0; cout = 1; end end else begin if(a==0 && b==0)begin sum = 1; cout = 0; end else if((a==0 && b==1) || (a==1 && b==0))begin sum = 0; cout = 1; end else begin sum = 1; cout = 1; end end end endmodule
//My Code module top_module ( input [31:0] a, input [31:0] b, output [31:0] sum );// wire carry1,carry2; wire [15:0] sum1; wire [15:0] sum2; add16 instance1(.a(a[15:0]),.b(b[15:0]),.cin(0),.cout(carry1),.sum(sum1)); add16 instance2(.a(a[31:16]),.b(b[31:16]),.cin(carry1),.cout(carry2),.sum(sum2)); assign sum = {sum2,sum1}; endmodule module add1 ( input a, input b, input cin, output sum, output cout ); // Full adder module here always @(*) begin sum = a^b^cin; cout = (a & b)|(a & cin)|(b & cin); end endmodule
027_Carry-Select Adder
module top_module( input [31:0] a, input [31:0] b, output [31:0] sum ); wire cout1,cout2,cout3; wire [15:0] sum1,sum2,sum3,sum_h; add16 instance1(.a(a[15:0]),.b(b[15:0]),.cin(0),.cout(cout1),.sum(sum1)); add16 instance2(.a(a[31:16]),.b(b[31:16]),.cin(0),.cout(cout2),.sum(sum2)); add16 instance3(.a(a[31:16]),.b(b[31:16]),.cin(1),.cout(cout3),.sum(sum3)); always @(*)begin case(cout1) 1:sum_h = sum3; 0:sum_h = sum2; endcase end assign sum = {sum_h,sum1}; endmodule
028_Adder-Subtractor
module top_module( input [31:0] a, input [31:0] b, input sub, output [31:0] sum ); wire cout1,cout2; wire [15:0] sum1,sum2; wire [31:0] b_xor ; always @(*) begin if(sub) b_xor = ~b; else b_xor = b; end add16 instance1(.a(a[15: 0]),.b(b_xor[15: 0]),.cin(sub),.sum(sum1),.cout(cout1)); add16 instance2(.a(a[31:16]),.b(b_xor[31:16]),.cin(cout1),.sum(sum2),.cout(cout2)); assign sum = {sum2,sum1}; endmodule
4_Procedures
029_Always Blocks(Combinational)
// synthesis verilog_input_version verilog_2001 module top_module( input a, input b, output wire out_assign, output reg out_alwaysblock ); assign out_assign = a & b; always @(*) out_alwaysblock = a & b; endmodule
030_Always Blocks(Clocked)
// synthesis verilog_input_version verilog_2001 module top_module( input clk, input a, input b, output wire out_assign, output reg out_always_comb, output reg out_always_ff ); assign out_assign = a^b; always @(*) out_always_comb = a^b; always @(posedge clk) out_always_ff = a^b; endmodule
031_If Statement
// synthesis verilog_input_version verilog_2001 module top_module( input a, input b, input sel_b1, input sel_b2, output wire out_assign, output reg out_always ); assign out_assign = (sel_b1 && sel_b2)?b:a; always @(*) out_always = (sel_b1 && sel_b2)?b:a; endmodule
032_If Statement Latches(😕)
// synthesis verilog_input_version verilog_2001 module top_module ( input cpu_overheated, output reg shut_off_computer, input arrived, input gas_tank_empty, output reg keep_driving ); // always @(*) begin if (cpu_overheated) shut_off_computer = 1; else shut_off_computer = 0; end always @(*) begin if (~arrived) keep_driving = ~gas_tank_empty; else keep_driving = 0; end endmodule
033_Case Statement Latches
// synthesis verilog_input_version verilog_2001 module top_module ( input [2:0] sel, input [3:0] data0, input [3:0] data1, input [3:0] data2, input [3:0] data3, input [3:0] data4, input [3:0] data5, output reg [3:0] out );// always@(*) begin // This is a combinational circuit case(sel) 3'b000:out = data0; 3'b001:out = data1; 3'b010:out = data2; 3'b011:out = data3; 3'b100:out = data4; 3'b101:out = data5; default out = 4'b0000; endcase end endmodule
034_Priority Encoder
// synthesis verilog_input_version verilog_2001 module top_module ( input [3:0] in, output reg [1:0] pos ); always @(*)begin case(in) 2:pos = 1; 4:pos = 2; 6:pos = 1; 8:pos = 3; 10:pos = 1; 12:pos = 2; 14:pos = 1; default pos = 0; endcase end endmodule
035_Priority Encoder With Casez
// synthesis verilog_input_version verilog_2001 module top_module ( input [7:0] in, output reg [2:0] pos ); always @(*)begin casez(in[7:0]) 8'bzzzzzzz1 : pos = 0; 8'bzzzzzz1z : pos = 1; 8'bzzzzz1zz : pos = 2; 8'bzzzz1zzz : pos = 3; 8'bzzz1zzzz : pos = 4; 8'bzz1zzzzz : pos = 5; 8'bz1zzzzzz : pos = 6; 8'b1zzzzzzz : pos = 7; default : pos = 0; endcase end endmodule
036_Avoiding Latches
// synthesis verilog_input_version verilog_2001 module top_module ( input [15:0] scancode, output reg left, output reg down, output reg right, output reg up ); always @(*)begin left = 0; right = 0; up = 0; down = 0; case(scancode) 16'he06b:left=1;// left arrow 16'he072:down=1;// down arrow 16'he074:right=1;// right arrow 16'he075:up=1;// up arrow default:;// None endcase end endmodule
5_More Verilog Features
037_Conditional Ternary Operator
module top_module ( input [7:0] a, b, c, d, output [7:0] min);// // assign intermediate_result1 = compare? true: false; wire[7:0] min1,min2,min3; assign min1 = a>b?b:a; assign min2 = min1>c?c:min1; assign min3 = min2>d?d:min2; assign min = min3; endmodule
038_Reduction Operators
module top_module ( input [7:0] in, output parity); assign parity = ^ in[7:0]; endmodule
⚠️ NO Figure Reply. I CAN get the all-mismatch answer.
# Hint: Output 'partity' has no mismatches. # Hint: Total mismatched samples is 0 out of 98 samples
039_Reduction: Even Wider Gates
module top_module( input [99:0] in, output out_and, output out_or, output out_xor ); assign out_and = & in[99:0]; assign out_or = | in[99:0]; assign out_xor = ^ in[99:0]; endmodule
040_Combinational For-Loop: Vector Reversal 2
module top_module( input [99:0] in, output [99:0] out ); always @(*) begin for(int i=0;i<100;i++) out[i] = in[99-i]; end endmodule
041_Combination For-Loop: 255-bit Population Count
module top_module( input [254:0] in, output [7:0] out ); always @(*)begin out = 0; for(int i=0;i<255;i++) out = out+in[i]; end endmodule
042_Generate For-Loop: 100-bit binary adder 2
module top_module( input [99:0] a, b, input cin, output [99:0] cout, output [99:0] sum ); assign cout[0] = (a[0]&b[0])|(a[0]&cin)|(b[0]&cin); assign sum[0] = a[0]^b[0]^cin; always @(*)begin for(int i=1;i<100;i++)begin cout[i] = (a[i]&b[i])|(a[i]&cout[i-1])|(b[i]&cout[i-1]); sum[i] = (a[i]^b[i]^cout[i-1]); end end endmodule
043_Generate For-Loop: 100-digit BCD adder
module top_module( input [399:0] a, b, input cin, output cout, output [399:0] sum ); wire [399:0] cout_tmp; bcd_fadd fadd(.a(a[3:0]), .b(b[3:0]), .cin(cin), .cout(cout_tmp[0]), .sum(sum[3:0])); assign cout = cout_tmp[396]; generate genvar i; for(i = 4; i < 400; i=i+4) begin : adder bcd_fadd fadd(.a(a[i+3:i]), .b(b[i+3:i]), .cin(cout_tmp[i-4]), .cout(cout_tmp[i]),.sum(sum[i+3:i])); end endgenerate endmodule