代码段
module Top (
input rst,
input CLK,
input Key,
output reg l1,
output reg l2,
output reg l3,
output reg l4,
output reg l5,
output reg l6,
output reg l7,
output reg l8
) ;
wire c1, key_p;
wire o1, o2, o3, o4, o5, o6, o7, o8;
Fdiv uu1 ( rst, CLK, 32 'd125000, c1) ;
XD uu2 ( rst, c1, Key, key_p) ;
LED uu3 ( rst, key_p, o1, o2, o3, o4, o5, o6, o7, o8) ;
always@( * ) begin
l1<= o1;
l2<= o2;
l3<= o3;
l4<= o4;
l5<= o5;
l6<= o6;
l7<= o7;
l8<= o8;
end
endmodule
module Fdiv (
input rst,
input clk_M,
input [ 31 : 0 ] k,
output reg clk
) ;
reg [ 31 : 0 ] cnt;
initial begin cnt= 32 'd0; end
initial begin clk= 0 ; end
always@( posedge rst, posedge clk_M) begin
if ( rst) begin
cnt<= 32 'd0;
clk<= 1 'b0;
end
else if ( cnt== k- 1 ) begin
cnt<= 32 'd0;
clk<= ~ clk;
end
else
cnt<= cnt+ 1 'b1;
end
endmodule
module XD (
input rst,
input clk,
input key,
output reg key_pulse
) ;
reg [ 2 : 0 ] ST;
parameter S0= 3 'b000,S1=3' b001, S2= 3 'b010,S3=3' b011, S4= 3 'b100,S5=3' b101;
initial begin ST= S0; end
always@( posedge rst or posedge clk) begin
if ( rst) begin
ST<= S0;
key_pulse<= 0 ;
end
else begin
case ( ST)
S0: ST<= key? S1: S0;
S1: ST<= key? S3: S2;
S2: ST<= key? S1: S0;
S3: ST<= key? S3: S4;
S4: ST<= key? S5: S0;
S5: ST<= key? S3: S4;
default ST<= S0;
endcase
if ( ST== S4|| ST== S5|| ST== S3) begin
key_pulse<= 1 ;
end
else key_pulse<= 0 ;
end
end
endmodule
module LED (
input rst,
input clk_t ,
output reg L1,
output reg L2,
output reg L3,
output reg L4,
output reg L5,
output reg L6,
output reg L7,
output reg L8
) ;
reg [ 7 : 0 ] cnt;
initial begin cnt= 8 'b00000000; end
initial begin L1= 0 ; L2= 0 ; L3= 0 ; L4= 0 ; L5= 0 ; L6= 0 ; L7= 0 ; L8= 0 ; end
always@( posedge rst or negedge clk_t ) begin
if ( rst) begin
cnt<= 8 'b00000000;
end
else if ( cnt== 8 'b11111111) begin
cnt<= 8 'b00000000;
L1<= 0 ;
L2<= 0 ;
L3<= 0 ;
L4<= 0 ;
L5<= 0 ;
L6<= 0 ;
L7<= 0 ;
L8<= 0 ;
end
else begin
cnt<= cnt+ 1 'b1;
L1<= cnt[ 0 ] ;
L2<= cnt[ 1 ] ;
L3<= cnt[ 2 ] ;
L4<= cnt[ 3 ] ;
L5<= cnt[ 4 ] ;
L6<= cnt[ 5 ] ;
L7<= cnt[ 6 ] ;
L8<= cnt[ 7 ] ;
end
end
endmodule
测试文件
module Test;
reg rst;
reg CLK;
reg Key;
wire l1;
wire l2;
wire l3;
wire l4;
wire l5;
wire l6;
wire l7;
wire l8;
Top uut (
. rst ( rst) ,
. CLK ( CLK) ,
. Key ( Key) ,
. l1 ( l1) ,
. l2 ( l2) ,
. l3 ( l3) ,
. l4 ( l4) ,
. l5 ( l5) ,
. l6 ( l6) ,
. l7 ( l7) ,
. l8 ( l8)
) ;
always #20 CLK= ~ CLK;
initial begin
rst = 0 ;
CLK = 0 ;
Key = 0 ;
#50000000 ;
Key= 0 ;
#50000000 ;
Key= 1 ;
#50000000 ;
Key= 0 ;
#50000000 ;
Key= 0 ;
#50000000 ;
Key= 1 ;
#50000000 ;
#5000000 ;
Key= 0 ;
#5000000 ;
Key= 1 ;
#5000000 ;
Key= 0 ;
#5000000 ;
Key= 0 ;
#5000000 ;
Key= 1 ;
#5000000 ;
Key= 0 ;
#5000000 ;
Key= 0 ;
#5000000 ;
Key= 1 ;
#5000000 ;
Key= 0 ;
Key= 0 ;
#50000000 ;
Key= 0 ;
#50000000 ;
Key= 1 ;
#50000000 ;
Key= 0 ;
#50000000 ;
Key= 0 ;
#50000000 ;
Key= 1 ;
#50000000 ;
Key= 0 ;
#50000000 ;
Key= 0 ;
#50000000 ;
Key= 1 ;
#50000000 ;
Key= 0 ;
end
endmodule
管脚配置
# PlanAhead Generated IO constraints
NET "CLK" IOSTANDARD = LVCMOS18;
NET "Key" IOSTANDARD = LVCMOS18;
NET "l1" IOSTANDARD = LVCMOS18;
NET "l3" IOSTANDARD = LVCMOS18;
NET "l2" IOSTANDARD = LVCMOS18;
NET "l4" IOSTANDARD = LVCMOS18;
NET "l5" IOSTANDARD = LVCMOS18;
NET "l6" IOSTANDARD = LVCMOS18;
NET "l7" IOSTANDARD = LVCMOS18;
NET "rst" IOSTANDARD = LVCMOS18;
NET "l8" IOSTANDARD = LVCMOS18;
# PlanAhead Generated physical constraints
NET "CLK" LOC = H4;
NET "Key" LOC = AA4;
NET "l1" LOC = R1;
NET "l2" LOC = P2;
NET "l3" LOC = P1;
NET "l4" LOC = N2;
NET "l5" LOC = M1;
NET "l6" LOC = M2;
NET "l7" LOC = L1;
NET "l8" LOC = J2;
NET "rst" LOC = R4;
# PlanAhead Generated IO constraints
NET "Key" PULLDOWN;
NET "rst" PULLDOWN;