Exams/2013 q2bfsm

Consider a finite state machine that is used to control some type of motor. The FSM has inputs x and y, which come from the motor, and produces outputs f and g, which control the motor. There is also a clock input called clk and a reset input called resetn.

The FSM has to work as follows. As long as the reset input is asserted, the FSM stays in a beginning state, called state A. When the reset signal is de-asserted, then after the next clock edge the FSM has to set the output f to 1 for one clock cycle. Then, the FSM has to monitor the x input. When x has produced the values 1, 0, 1 in three successive clock cycles, then g should be set to 1 on the following clock cycle. While maintaining g = 1 the FSM has to monitor the y input. If y has the value 1 within at most two clock cycles, then the FSM should maintain g = 1 permanently (that is, until reset). But if y does not become 1 within two clock cycles, then the FSM should set g = 0 permanently (until reset).

(The original exam question asked for a state diagram only. But here, implement the FSM.)

module top_module (
    input clk,
    input resetn,    // active-low synchronous reset
    input x,
    input y,
    output f,
    output g
); 
    parameter [3:0]idle=4'd1;
    parameter [3:0]bit1=4'd2;
    parameter [3:0]bit2=4'd3;
    parameter [3:0]bit3=4'd4;
    parameter [3:0]yit0=4'd5;
    parameter [3:0]yit1=4'd6;
    parameter [3:0]yit2=4'd7;
    parameter [3:0]af=4'd8;
    parameter [3:0]a=4'd0;
 

    reg [3:0]state,next_state;
    always@(posedge clk)begin
        if(!resetn)
            state<=a;
        else
            state<=next_state;
    end
    
    always@(*)begin
           next_state<=a;
        case(state)
        a:next_state<=af;
        af:next_state<=idle;
        idle:next_state<=x?bit1:idle;
        bit1:next_state<=x?bit1:bit2;
        bit2:next_state<=x?bit3:idle;
        bit3:next_state<=y?yit0:yit1;
        yit1:next_state<=y?yit0:yit2;
        yit0:next_state<=yit0;
        yit2:next_state<=yit2;
         default:next_state<=a;
        endcase
    end
    
    
    assign f=(state==af);
   assign g=(state==bit3)|(state==yit0)|(state==yit1);
   /* always@(*) begin
        if((state==bit3)||(state==yit0)||(state==yit1))
            g = 1;
		else 
            g = 0;
    end
// output f
    always@(*) begin
        f = (state==af);
    end*/
        
endmodule

 一定要读懂题目,然后进行状态分析.