FPGA project : breath_led

 

module breath_led
#(
    parameter    CNT_1US =  6'd50    ,
    parameter    CNT_1K  = 10'd1000 
)(
    input               wire        sys_clk     ,
    input               wire        sys_rst_n   ,

    output              reg         led_out
);
    // signal define
    reg     [05:00]     cnt_1us ;
    wire                add_cnt_1us ;
    wire                end_cnt_1us ;
    
    reg     [09:00]     cnt_1ms ;
    wire                add_cnt_1ms ;
    wire                end_cnt_1ms ;
    
    reg     [09:00]     cnt_1s ;
    wire                add_cnt_1s ;
    wire                end_cnt_1s ;

    reg                 ctrl       ;
    // cnt_1us 每计数一次 是20ns ; 计满为 1us ;
    always @(posedge sys_clk or negedge sys_rst_n) begin
        if(~sys_rst_n) begin
            cnt_1us <= 0 ;
        end else begin
            if(add_cnt_1us) begin
                if(end_cnt_1us) begin
                    cnt_1us <= 0 ;
                end else begin
                    cnt_1us <= cnt_1us + 1'b1 ;
                end
            end else begin
                cnt_1us <= cnt_1us ;
            end
        end
    end
    assign add_cnt_1us = 1'b1 ;
    assign end_cnt_1us = add_cnt_1us && cnt_1us == ( CNT_1US - 1'b1 ) ;

    // cnt_1ms 每计数一次 是1us ; 计满为 1ms ;
    always @(posedge sys_clk or negedge sys_rst_n) begin
        if(~sys_rst_n) begin
            cnt_1ms <= 0 ;
        end else begin
            if(add_cnt_1ms) begin
                if(end_cnt_1ms) begin
                    cnt_1ms <= 0 ;
                end else begin
                    cnt_1ms <= cnt_1ms + 1'b1 ;
                end
            end else begin
                cnt_1ms <= cnt_1ms ;
            end
        end
    end
    assign add_cnt_1ms = end_cnt_1us ;
    assign end_cnt_1ms = add_cnt_1ms && cnt_1ms == ( CNT_1K - 1'b1 ) ;

    // cnt_1s 每计数一次 是1ms ; 计满为 1s ;
    always @(posedge sys_clk or negedge sys_rst_n) begin
        if(~sys_rst_n) begin
            cnt_1s <= 0 ;
        end else begin
            if(add_cnt_1s) begin
                if(end_cnt_1s) begin
                    cnt_1s <= 0 ;
                end else begin
                    cnt_1s <= cnt_1s + 1'b1 ;
                end
            end else begin
                cnt_1s <= cnt_1s ;
            end
        end
    end
    assign add_cnt_1s = end_cnt_1ms ;
    assign end_cnt_1s = add_cnt_1s && cnt_1s == ( CNT_1K - 1'b1 ) ;

    // ctrl
    always @(posedge sys_clk or negedge sys_rst_n) begin
        if(~sys_rst_n) begin
            ctrl <= 1'b1 ;
        end else begin
            if(end_cnt_1s) begin
                ctrl <= ~ctrl ;
            end else begin
                ctrl <=  ctrl ;
            end
        end
    end
    // led_out
    always @(posedge sys_clk or negedge sys_rst_n) begin
        if(~sys_rst_n) begin
            led_out <= 1'b1 ;
        end else begin
            if(ctrl) begin
                if( cnt_1s > cnt_1ms ) begin
                    led_out <= 1'b0 ;
                end else begin
                    led_out <= 1'b1 ;
                end
            end else begin
                if( cnt_1s > cnt_1ms ) begin
                    led_out <= 1'b1 ;
                end else begin
                    led_out <= 1'b0 ;
                end
            end
        end
    end
endmodule

 

`timescale 1ns/1ns
module test();
    reg                      sys_clk     ;
    reg                      sys_rst_n   ;
    wire                     led_out     ;

// Instantiation
breath_led
#(
    .CNT_1US                ( 10        ) ,
    .CNT_1K                 ( 100       ) 
)
breath_led_insert
(
    .sys_clk                ( sys_clk   ) ,
    .sys_rst_n              ( sys_rst_n ) ,

    .led_out                ( led_out   )
);
    parameter CYCLE = 20 ;

    initial begin
        sys_clk    = 1'b1 ;
        sys_rst_n <= 1'b0 ;
        #( CYCLE * 10 )   ;
        sys_rst_n <= 1'b1 ;
        #( 210 )          ;
        sys_rst_n <= 1'b0 ;
        #( CYCLE * 10 )   ;
        sys_rst_n <= 1'b1 ;
        #( CYCLE * 1000 ) ;
    end

    always #( CYCLE / 2 ) sys_clk = ~sys_clk ;


endmodule