Verilog_initial里面的语句能综合吗？如何写自reset的可综合代码

不一定能综合：

initial
begin
    CONV_iData0 = 8'h01;
    CONV_iData1 = 8'h01;
end

综合之后用RTLViewer一看：

根本没有连接，但是在用上以下的操作之后：

parameter Rst0State = 2'b00;
parameter Rst1State = 2'b01;
parameter WorkState = 2'b10;
    
reg reset;
reg clk;
reg  [7:0] CONV_iData0;
reg  [7:0] CONV_iData1;
reg  [1:0] State;
  
always @(posedge clk)
begin
	if(State == Rst0State)//开始复位
	begin		
		reset <= 0;
		index_reset <= 0;
		State <= Rst1State;
	end
	else 
	if(State == Rst1State)//保持复位，复位结束
		begin
			if(index_reset <= 16'hfe)
			begin
				index_reset <= index_reset + 1;
			end
			else
			begin
				//index_reset <= 0;
				State <= WorkState;
				reset <= 1;
			end
		end
		else
			if(State == WorkState)//输入数据
			begin
				reset <= 1;
				State <= WorkState;
				CONV_iData0 = 8'h01;
				CONV_iData1 = 8'h01;
			end
end

就可以给两条iData线真的进行连接了，而且状态机还包括reset的输出：