轻量级开源Verilog编译仿真工具 Icarus Verilog + GTKWave 简单体验

前言

最近整了个Surface Go，这东西非常轻便，玩玩Narrative Game、Galgame啥的还挺不错的。不过性能比较孱弱，偶尔想要本地编译仿真下Verilog，装主流的开发环境还是太勉强了，搞点轻量级的用用还可以。本文主要体验下 Icarus Verilog + GTKWave 这个组合。

工具介绍

Icarus Verilog是一个轻量级的Verilog编译器，可以编译Verilog代码并运行仿真。

项目地址：https://github.com/steveicarus/iverilog
文档主页：https://steveicarus.github.io/iverilog/

Icarus Verilog is intended to compile ALL of the Verilog HDL, as described in the IEEE 1364 standard. Of course, it’s not quite there yet. It also compiles a (slowly growing) subset of the SystemVerilog language, as described in the IEEE 1800 standard.

Icarus Verilog is not aimed at being a simulator in the traditional sense, but a compiler that generates code employed by back-end tools.

Icarus Verilog只是编译和运行仿真，是无法查看仿真输出的波形图的，这个时候就需要用GTKWave来查看了。

项目地址：https://github.com/gtkwave/gtkwave

GTKWave is a fully featured wave viewer based on GTK for Unix, Win32, and Mac OSX. It supports various file formats including FST, LXT, LXT2, VZT, GHW, and standard Verilog VCD/EVCD files. Primarily used for debugging Verilog or VHDL simulation models, GTKWave is designed for post-mortem analysis by analyzing dumpfiles rather than real-time interaction during simulations. It allows the visualization of both analog and digital data, supports various search operations, and enables users to save “signals of interest” extracted from a complete simulation dump. Additionally, GTKWave can generate outputs in PostScript and FrameMaker formats for hard copy documentation.

工具使用

Icarus Verilog 和 GTKWave 都是需要自行编译才能使用的，不过网上也有直接编译打包了可以在Windows上使用的版本：
https://bleyer.org/icarus/ （目前最新版本为 iverilog-v12-20220611-x64_setup [18.2MB] ）

下载后直接安装就行，安装时选择添加到环境变量：

Icarus Verilog 和 GTKWave 的使用可以参考官方文档说明。下面进行简单的演示：

上面使用 iverilog -o mux_2_to_1 -c file_list.txt 进行编译， -o 用于指定编译生成的文件名， -c 用于指定需要编译的文件的文件列表。

需要注意的是仿真文件中需要有下面代码，这样后面运行仿真时才能生成波形文件：

/* iverilog */
initial begin            
    $dumpfile("wave.vcd"); // 生成的vcd文件名称
    $dumpvars(0, mux_2_to_1_tb); // tb模块名称
end
/* iverilog */

上面使用 vvp -n mux_2_to_1 -lxt2 运行仿真，根据前面添加的仿真脚本，这里同时会生成波形文件。

上面使用 gtkwave wave.vcd 来查看波形文件。打开界面后需要手动加载信号才会在波形窗口显示。

Verilator

Icarus Verilog只是一般的简单编译验证用用还不错，如果需要用在大型项目那么它的性能就不够了，编译仿真会很慢，这个时候还可以选择 Verilator ，不过同样需要自己编译。

官方页面：https://www.veripool.org/verilator/
项目地址：https://github.com/verilator/verilator

Verilator is invoked with parameters similar to GCC or Synopsys’s VCS. It “Verilates” the specified Verilog or SystemVerilog code by reading it, performing lint checks, and optionally inserting assertion checks and coverage-analysis points. It outputs single- or multithreaded .cpp and .h files, the “Verilated” code.

These Verilated C++/SystemC files are then compiled by a C++ compiler (gcc/clang/MSVC++), optionally along with a user’s own C++/SystemC wrapper file, to instantiate the Verilated model. Executing the resulting executable performs the design simulation. Verilator also supports linking Verilated generated libraries, optionally encrypted, into other simulators.

Verilator may not be the best choice if you are expecting a full-featured replacement for a closed-source Verilog simulator, need SDF annotation, mixed-signal simulation, or are doing a quick class project (we recommend Icarus Verilog for classwork). However, if you are looking for a path to migrate SystemVerilog to C++/SystemC, or want high-speed simulation of designs, Verilator is the tool for you.

后记

传统的Verilog工具都比较重，Icarus这种轻量化的用用有时候蛮方便的，适合临时的、碎片化的使用。