module test_bidata;
reg clk;
reg z;
reg[15:0]din;
wire[15:0]dout;
wire[15:0]dinout;
integer i;
bidirec_data uut(
.din(din),
.z(z),
.clk(clk),
.dout(dout),
.dinout(dinout),
);
always #10 clk=~clk;
initial begin
z=1;
clk=0;
din=0;
force dinout=20;
#200 for(i=0;i<10;i=i+1)
#20 force dinout=dinout-1;
end
always #20din=din+1;
reg clk;
reg z;
reg[15:0]din;
wire[15:0]dout;
wire[15:0]dinout;
integer i;
bidirec_data uut(
.din(din),
.z(z),
.clk(clk),
.dout(dout),
.dinout(dinout),
);
always #10 clk=~clk;
initial begin
z=1;
clk=0;
din=0;
force dinout=20;
#200 for(i=0;i<10;i=i+1)
#20 force dinout=dinout-1;
end
always #20din=din+1;
endmodule
改为:
module test_bidata;
reg clk;
reg z;
reg[15:0]din;
wire[15:0]dout;
wire[15:0]dinout;
integer i;
always #10 clk=~clk;
initial begin
z=1;
clk=0;
din=0;
force dinout=20;
#200 for(i=0;i<10;i=i+1)
#20 force dinout=dinout-1;
end
always #20din=din+1;
endmodule
目前知道问题所在,具体原因弄懂了,再来叙述原因。