STM32F1XX嵌套中断向量控制器（NVIC）与相关寄存器

Nested vectored interrupt controller=NVIC

STM32F1xx的中断

CortexM3允许16个内核中断异常和240个外部中断输入。

手头所使用的stm32f103支持16个内核中断异常和60个外部可屏蔽中断线。同时引入中断分级和嵌套中断管理机制。

• 68 (not including the sixteen Cortex®-M3 interrupt lines)
• 16 programmable priority levels (4 bits of interrupt priority are used)
• Low-latency exception and interrupt handling
• Power management control
• Implementation of System Control registers

The NVIC and the processor core interface are closely coupled, which enables low latency interrupt processing and efficient processing of late arriving interrupts.All interrupts including the core exceptions are managed by the NVIC. For more information on exceptions and NVIC programming, refer to STM32F10xxx Cortex®-M3 programming manual

The STM32F103xC, STM32F103xD and STM32F103xE performance line embeds a nested vectored interrupt controller able to handle up to 60 maskable interrupt channels (not including the 16 interrupt lines of Cortex®-M3) and 16 priority levels.

何为中断分级与嵌套中断管理

STM32的中断有两套分级：主优先级/抢占优先级（group priority）和次优先级/响应优先级（subpirority），对于两套优先级有以下的机制：

1. 高抢占优先级的中断可以打断低抢占优先级的中断。
2. 相同抢占优先级的中断，高相应优先级的中断无法打断低相应优先级的中断，二者同时发生的时候高相应优先级的中断先执行。
3. 抢占优先级和相应优先级都相同的的两个中断同时发生，个即异常向量表*中的顺序决定先处理哪一个。

*注下为异常向量表：

那么何为嵌套中断？这就是应用了上述第一点的中断机制，即高抢占优先级中断程序可以在低抢占优先级中断程序运行过程中插入运行，等高优先级的程序运行结束后CPU又回过头来运行低优先级中断程序。

To increase priority control in systems with interrupts, the NVIC supports priority grouping. This divides each interrupt priority register entry into two fields:

• An upper field that defines the group priority
• A lower field that defines a subpriority within the group.

Only the group priority determines preemption of interrupt exceptions. When the processor is executing an interrupt exception handler, another interrupt with the same group priority as the interrupt being handled does not preempt the handler,If multiple pending interrupts have the same group priority, the subpriority field determines the order in which they are processed. If multiple pending interrupts have the same group priority and subpriority, the interrupt with the lowest IRQ number is processed first.

NVIC相关寄存器

SCB_AIRCR

用来设置该SOC的NVIC分级策略

PRIGROUP 10:8：分组模式位，决定中断的抢占优先级与响应优先级的组合方式：

PRIGROUP三位的值	IP寄存器中抢占优先级的位数	IP寄存器中响应优先级的位数	抢占优先级分级量	响应优先级分级量
111	4位，[7:4]	0位	16	none
100	3位，[7:5]	1位，[4]	8	2
101	2位，[7:6]	2位，[5:4]	4	4
110	1位，[7]	3位，[6:4]	2	8
111	0位	4位，[7:4]	none	16

NVIC_IPRx

用来设置每一个中断的分级。

IPR0寄存器为IP[3]~IP[0] 每一个IP有8bit，以此类推IPR16为IP[67]_{IP[64],即IPRm为IP[4m+3]}IP[4m],每一组IP有8bit，管理着一条中断线也就是对应着一个中断， [7:4]为有效分级位，[3:0]为无效保留位。

Each priority field holds a priority value, 0-255. The lower the value,the greater the priority of the corresponding interrupt. The processor implements only bits[7:4] of each field, bits[3:0] read as zero and ignore writes.

ISERx&ICERx&IABRx

ISER中断使能寄存器，ICER中断失能寄存器，IABR中断活动寄存器。

每一位代表着每一个对应中断的使能，失能，IABR为只读寄存器，每一位代表着对应中断正在中断。

mapping of interrupts to the interrupt variables;

interrupt	set_enable	clear_enable	set-pending	clear-pending	active bit
0-31	ISER0	ICER0	ISPR0	ICPR0	IABR0
32-63	ISER1	ICER1	ISPR1	ICPR1	IABR1
64-67	ISER2	ICER2	ISPR2	ICPR2	IABR2