来源:systemverilog验证 测试平台编写指南(书籍)
1 新建factorial.c文件
vi factorial.c
int factorial (int i) {
if (i <= 1) return i;
else return i*factorial(i-1);
}
2 新建test.sv文件
vi test.sv
import "DPI-C" function int factorial(input int i);
program automatic test;
initial begin
for (int i; i <= 10; i++)
$display ("%0d! = %0d", i, factorial(i));
end
endprogram
3 制作makefile
vi makefile
run: vcs sim
vcs:
vcs -full64 -sverilog test.sv factorial.c
sim:
./simv
clean:
rm -f simv novas.conf *.log *.dump *.rc *.key test.fsdb
rm -rf csrc/ simv.daidir/ verdiLog/
4 输入 make run 即可有以下结果