vivado xdc约束基础知识0：常用命令

先简单描述常用命令，后续将详细介绍。

1. 外部时钟输入的约束如下：

create_clock -period (clock period) -name (clock name) -waveform { (Traise), (Tfall) } [get_ports (clock port name)]

2. 已建立的时钟改名

create_generated_clock -name (clock name) [get_pins (path)]

3.input/output delay 设置
set_input_delay    -clock [get_clocks (clock name)] (delay time ns)  [all inputs]
set_output_delay -clock [get_clocks (clock name)]  (delay time ns) [all outputs]

4. 建立时钟组
set_clock_groups -name (group name) -asynchronous -group {(clock name) (clock name) }

set_clock_groups -name (group name) -asynchronous -group [get_clocks (clock name)]

5. 管脚分配
set_property PACKAGE_PIN (pin location) [get_ports (port name)]
set_property IOSTANDARD (level:LVDS,LVCMOS18,LVCMOS33 etc.) [get_ports (port name)]

6. 管脚作为时钟线

set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets (port_name)]

7. 管脚拉高

set_property PULLUP true [get_ports (port name)]

8. 当 vivado 报错说有某些管脚没有分配时，加下面两句
set_property SEVERITY {Warning} [get_drc_checks NSTD-1]

set_property SEVERITY {Warning} [get_drc_checks UCIO-1]