Verilog 实现二输入选择器

Verilog 实现二输入选择器

// An highlighted block
var foo = 'bar';
方法一： if ……else

module selector_21(s, a, b, y);
    input s;
    input a;
    input b;
    
    output reg y;
    
    //行为建模：组合逻辑电路
    always @ (*)    begin
        if (s)
        y = a;
        else
        y = b;
    end
 endmodule


方法二： case
 module selector_21(s, a, b, y);
    input s;
    input a;
    input b;
    
    output reg y;
    
    //行为建模：组合逻辑电路
    always @ (*)    begin
        case(s)
        1'b0 : y = a;
        1'b1 : y = b;
        
        endcase
    end
   endmodule


Testbench文件
`timescale 1ns/1ps
module selector_21_tb;
    
    reg s;
    reg a;
    reg b;
    
    wire y;

    selector_21 selector_21_inst(
    .s(s), 
    .a(a), 
    .b(b), 
    .y(y)
    );
   
    initial begin
          s = 1;a = 0;b = 0;
    #200  s = 1;a = 0;b = 1;
    #200  s = 1;a = 1;b = 0;
    #200  s = 1;a = 1;b = 1;
    
    #200  s = 0;a = 0;b = 1;
    #200  s = 0;a = 1;b = 0;
    #200  s = 0;a = 1;b = 1;
    #200  s = 0;a = 1;b = 1;
   
    end
endmodule