Verilog实现38译码器

Verilog实现38译码器

// An highlighted block
var foo = 'bar';

module decode_38(date_in, date_out);
    
    input [2:0] date_in;        //date_in[2],date_in[1],date_in[0]
    output reg [7:0] date_out; 
    
    //行为建模：组合逻辑电路
    always @ (*)    begin
        case(date_in)                 //case语句：括号为输入的条件
           3'd0     : date_out = 8'b0000_0001;
           3'd1     : date_out = 8'b0000_0010;
           3'd2     : date_out = 8'b0000_0100;
           3'd3     : date_out = 8'b0000_1000;
           
           3'd4     : date_out = 8'b0001_0000;
           3'd5     : date_out = 8'b0010_0000;
           3'd6     : date_out = 8'b0100_0000;
           3'd7     : date_out = 8'b1000_0000;
        endcase
    end
    
endmodule

// An highlighted block
var foo = 'bar';
`timescale 1ns/1ps
module decode_38_tb;

    reg [2:0] date_in;        //date_in[2],date_in[1],date_in[0]
    wire[7:0] date_out;
    
    decode_38 decode_38_inst(
        .date_in(date_in), 
        .date_out(date_out)
    );

   //port
   initial begin
          date_in = 3'b000;
    #200  date_in = 3'b001;
    #200  date_in = 3'b010;
    #200  date_in = 3'b011;
    #200  date_in = 3'b100;
    #200  date_in = 3'b101;
    #200  date_in = 3'b110;
    #200  date_in = 3'b111;
   end
endmodule