Verilog语言要素（一）

1 Verilog语言要素

1.1 空白-注释-操作符

1.1.1 空白(White Space)

规范原文如下：

1. White space shall contain the characters for spaces, tabs, newlines, and formfeeds. – 空白包括空白格、空白行、制表符、换行符、换页符
2. These characters shall be ignored except when they serve to separate other lexical tokens.
3. However, blanks and tabs shall be considered significant characters in strings. – 空白格和制表符在字符串中不能被忽略

1.1.2 注释(Comment)

规范原文如下：

1. The Verilog HDL has two forms to introduce comments.
2. A one-line comment shall start with the two characters // and end with a newline. – 行注释只能注释一行代码
3. A block comment shall start with /* and end with */ and shall not be nested. – 块注释可以注释多行代码但不可嵌套

1.1.3 操作符(Operator)

规范原文如下：

1. Operators are single-, double-, or triple-character sequences and are used in expressions.
2. Unary operators shall appear to the left of their operand. – 单目操作符
3. Binary operators shall appear between their operands. – 双目操作符
4. A conditional operator shall have two operator characters that separate three operands. – 条件操作符是唯一的三目操作符