Primary Clocks
Vivado自动从设计中推断出主时钟:
1. The wizard automatically identifies the proper clock source point for the constraint.
哪些时钟会被推断成主时钟呢?
1. In most cases, the clock source point is an input clock port.
2. In some special cases it is the output of a primitive that does not have a timing arc.
总结就是:
1. 时钟输入管脚(Port)
2. GT_CHANNEL时钟输出引脚(TXOUTCLK、RXOUTCLK)
(1)For 7 series devices, the wizard identifies missing primary clocks on the output of GT_CHANNEL primitives.
(2)For UltraScale™ devices, the Vivado Design Suite is able to auto-derive the GT_CHANNEL output clocks.
(3)对于7系列FPGA,GT_CHANNEL的输出时钟TXOUTCLK和RXOUTCLK会被Vivado推断为主时钟。
(4)对于U系列FPGA,GT_CHANNEL的输出时钟TXOUTCLK和RXOUTCLK会被Vivado推断为自动生成时钟。
以Vivado自带的CPU Example Design为例:
Generated Clocks
Vivado自动从设计中推断出生成时钟:
1. The Timing Constraints wizard recommends the creation of a generated clock on the output of a sequential cell when it drives the clock pins of other sequential cells either directly or through some interconnect logic.
典型案例就是CMB(Clock Modifying Block)自动生成的时钟,但是这些时钟不会出现在Timing Constraints Wizard中。
Forwarded Clocks
Vivado自动从设计中推断出伴随时钟:
1. The Timing Constraints wizard recommends generated clock constraints on output ports that are driven by double data-rate registers with constant inputs.
2. The master clock used in the constraint is the clock that reaches the clock pin of the double data-rate register.
伴随时钟是生成时钟的一种,哪些时钟会被推断成生成时钟呢?
1. 通过ODDR原语输出的时钟;
2. ODDR原语的输入(D1/D2)必须为常值。
Xilinx 7系列和Ultrascale系列FPGA的ODDR略有不同:
1、原语不同
7系列:
ODDR #(
.DDR_CLK_EDGE ("OPPOSITE_EDGE"), // "OPPOSITE_EDGE" or "SAME_EDGE"
.INIT (1'b0 ), // Initial value of Q: 1'b0 or 1'b1
.SRTYPE ("SYNC" ) // Set/Reset type: "SYNC" or "ASYNC"
) ODDR_inst (
.Q (o_clk), // 1-bit DDR output
.C (i_clk), // 1-bit clock input
.CE (1'B1 ), // 1-bit clock enable input
.D1 (1'B1 ), // 1-bit data input (positive edge)
.D2 (1'B0 ), // 1-bit data input (negative edge)
.R (1'B0 ), // 1-bit reset
.S (1'B0 ) // 1-bit set
);
U系列:
ODDRE1 #(
.IS_C_INVERTED (1'b0 ), // Optional inversion for C
.IS_D1_INVERTED (1'b0 ), // Unsupported, do not use
.IS_D2_INVERTED (1'b0 ), // Unsupported, do not use
.SIM_DEVICE ("ULTRASCALE"), // Set the device version
.SRVAL (1'b0 ) // Initializes the ODDRE1 Flip-Flops to the specified value (1'b0, 1'b1)
)
ODDRE1_inst (
.Q (o_clk), // 1-bit output: Data output to IOB
.C (i_clk), // 1-bit input: High-speed clock input
.D1 (1'B1 ), // 1-bit input: Parallel data input 1
.D2 (1'B0 ), // 1-bit input: Parallel data input 2
.SR (1'B0 ) // 1-bit input: Active High Async Reset
);
2、命令不同
7系列:
U系列:
总结如下:两者的差别主要在于source选项上,7系列是C,U系列是CLKDIV,相见"3、原理图不同"部分。
7系列:
create_generated_clock -name o_clk -source [get_pins ODDR_inst/C] -divide_by 1 [get_ports o_clk]
U系列:
create_generated_clock -name o_clk -source [get_pins ODDRE1_inst/CLKDIV] -divide_by 1 [get_ports o_clk]
3、原理图不同
7系列:
U系列:
从原理图可以看出7系列和U系列在实现ODDR的时候差别还是比较大的,详情参见Xilinx ug471和ug571。