FPGA常用小功能的代码

本篇文章仅供自己记录一些FPGA实现代码，若有不正确或不严谨的地方欢迎批评指正。

1、并转串的实现

//本代码选自以往工程，信号名称等不是重点，重点是实现思路
//设置一个移位寄存器，高位先入
    always @ (posedge CpSl_Clk_i) begin
        if (CpSl_Rst_i == 1'b1) begin
            PrSv_FrCntShift_s <= 6'd0;
        end
        else begin
            if (PrSv_FifoRdCnt_s == 8'd9)
			    PrSv_FrCntShift_s <= PrSv_BCCHFrCnt_s;
			else if (PrSv_FifoRdCnt_s <= 8'd15 && PrSv_FifoRdCnt_s >= 8'd10)
			    PrSv_FrCntShift_s <= {PrSv_FrCntShift_s[4:0],1'b0};//关键在于此行，移位寄存
			else;//hold 
        end
    end

//每次串行输出只取移位寄存器的最高位
	always @ (posedge CpSl_Clk_i) begin
        if (CpSl_61d44MRst_i == 1'b1) begin
            CpSl_Dout_o    <= 1'd0;
        end
        else begin
			if (PrSv_FifoRdCnt_s <= 8'd15 && PrSv_FifoRdCnt_s >= 8'd10) begin
			    if (PrSl_TxEn == 1'b1)
				    CpSl_Dout_o <= PrSl_FifoRdData_s;
				else
				    CpSl_Dout_o <= PrSv_FrCntShift_s[5];//对移位寄存的数据取先入的高位
			end
			else
			    CpSl_Dout_o <= PrSl_FifoRdData_s;   
        end
    end

2、串转并的实现

//本代码选自以往工程，信号名称定义等不是重点，重点是实现思路
//将串行输入的数据，变成并行65bits，左移高位先入
    always @ (posedge CpSl_Clk_i) begin
        if (CpSl_Rst_i == 1'b1) begin
            PrSv_DinVld_s <= 65'd0;
            PrSv_Din_s    <= 65'd0;
        end
        else begin
            PrSv_DinVld_s <= {PrSv_DinVld_s[63:0],CpSl_DinVld_i};
            PrSv_Din_s    <= {PrSv_Din_s[63:0],   CpSl_Din_i   };
        end
    end

3、计数器的实现

//第一种：记到4，则2bits满表示为4，位宽即可限制计数长度	
    always @ (posedge CpSl_Clk_i) begin
        if (CpSl_Rst_i == 1'b1) begin
            PrSv_AddZeroCnt_s <= 2'd0;
        end
        else begin
		    if (PrSl_AddZeroVld_s == 1'b1)
			    PrSv_AddZeroCnt_s <= PrSv_AddZeroCnt_s + 1'b1;
			else
			    PrSv_AddZeroCnt_s <= 2'd0;
        end
    end	

//第二种：位宽记满比计数长度大的，需要定义一个参数指示计数长度
    parameter       PrSv_DataIniLen_c = 8'd28              ;

    always @ (posedge CpSl_DataClk_i) begin
        if (CpSl_Rst_i == 1'b1) begin
            PrSv_DataVldCnt_s <= 8'd0;
        end
        else begin
		    if (CpSl_DataVld_i == 1'b1) begin
                if (PrSv_DataVldCnt_s == PrSv_DataIniLen_c - 1'b1)
                    PrSv_DataVldCnt_s <= 8'd0;
                else
                    PrSv_DataVldCnt_s <= PrSv_DataVldCnt_s + 1'b1;
            end
            else
                PrSv_DataVldCnt_s <= 8'd0;
        end
    end

4、数据延迟

// 可以通过上述计数器控制，当延迟拍数少时也直接通过赋值实现数据延迟
    always @(posedge CpSl_DataClk_i) begin
        if (CpSl_Rst_i == 1'b1) begin   
            PrSv_BmSDCCHDataDly1_s <= 8'd0;
			PrSv_BmSDCCHDataDly2_s <= 8'd0;
			PrSv_BmSDCCHDataDly3_s <= 8'd0;
        end
		else begin
            PrSv_BmSDCCHDataDly1_s <= CpSv_BmSDCCHData_i;
			PrSv_BmSDCCHDataDly2_s <= PrSv_BmSDCCHDataDly1_s;
			PrSv_BmSDCCHDataDly3_s <= PrSv_BmSDCCHDataDly2_s;
        end
    end

//当要延迟的拍数很多时，也可以通过通过循环的方法控制，本质与直接赋值一样
    genvar dly_cnt;
    generate for (dly_cnt = 0; dly_cnt < 96; dly_cnt = dly_cnt + 1) begin : Dly
        always @ (posedge CpSl_Clk_i) begin
            if(CpSl_Rst_i == 1'b1) begin
                PrSv_DinIDly_s       [dly_cnt] <= 16'd0;
                PrSv_DinQDly_s       [dly_cnt] <= 16'd0;
                PrSv_DinVldCntDly_s  [dly_cnt] <= 11'd0;
            end
            else begin
            if (dly_cnt == 0) begin
				    if (PrSl_DinVld_s == 1'b1) begin 
                        PrSv_DinIDly_s  [dly_cnt] <= PrSv_DinI_s;  
                        PrSv_DinQDly_s  [dly_cnt] <= PrSv_DinQ_s;   
                        PrSv_DinVldCntDly_s[dly_cnt] <= PrSv_DinVldCnt_s; 
					end
					else;//hold
            end
            else begin
				    if (PrSl_DinVld_s == 1'b1) begin 
                        PrSv_DinIDly_s  [dly_cnt]    <= PrSv_DinIDly_s  [dly_cnt - 1];
                        PrSv_DinQDly_s  [dly_cnt]    <= PrSv_DinQDly_s  [dly_cnt - 1];
                        PrSv_DinVldCntDly_s[dly_cnt] <= PrSv_DinVldCntDly_s  [dly_cnt - 1];
					end
					else;//hold
                end
            end
        end
    end
    endgenerate

5、数据缓存

// 5、输入数据及数据有效信号缓存，也可实现数据延迟，比如需要延迟4拍，则可以先缓存4拍数据，最后取第一拍输入的数据输出
    always @ (posedge CpSl_DataClk_i) begin
        if (CpSl_Rst_i == 1'b1) begin
            PrSv_BmData_s     <= 32'd0;
            PrSv_BmDataVld_s  <= 4'd0;
        end
        else begin
            PrSv_BmData_s     <= {PrSv_BmData_s[23:0],CpSv_BmBCCHData_i};
            PrSv_BmDataVld_s  <= {PrSv_BmDataVld_s[2:0],CpSl_BmBCCHDataVld_i};
        end
    end	
	
    assign CpSl_DataVld_o    = PrSl_Tx1FFlag_s ? PrSv_BmDataVld_s[3] : PrSl_RamRdVld0_s;
    assign CpSv_Data_o       = PrSl_Tx1FFlag_s ? PrSv_BmData_s[31:24]: PrSv_RamRdData0_s;